Attention is currently required from: Angel Pons.
4 comments:
Commit Message:
Patch Set #1, Line 9: any features
_NATIVE is already a set of features, namely 4BA read (0x13), fast read (0x0c)
and write (0x12) instructions.
Patch Set #1, Line 12: so select them through `FEATURE_4BA_EAR7`. As it is not known how this
It looks like they use different opcodes, though (16/17 instead of
the supported c5/c8). Which might be the original reason why it was
left out :-/
It might not be worth to add support for this untested. Dunno. If
we decide against it, I can add a comment why the entry looks so odd.
Patch Set #1, Line 13: chip definition could actually work, it has been marked as untested.
Only a programmer that can't send 4-byte addresses or restricts the
commands that can be send would have failed, AFAICS.
File flashchips.c:
Patch Set #1, Line 16732: }, {
Here is the actual issue why I put the entry on my release preparations
list. spi_block_erase_dc() would fail if the programmer doesn't support
4-byte addresses. Then, flashrom would automatically try to fall back
to the next eraser and erase the whole chip. It wouldn't be fatal,
just very inconvenient to wait for 64MiB to be erased.
Well, that was my assessment. It's not 100% correct. I guess flashrom
would bail out trying to read the chip already ;)
*scrolling noises*
The datasheet I found (Cypress, Document Number: 001-98284 Rev. *P,
Revised June 22, 2018) also mentions 0xd8 for the same block size
but as 3BA or 4BA command, depending on EAR7 (if we would support it
with the 0x16/0x17 commands).
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