Nico Huber has uploaded this change for review.
sb600spi: Add support for Merlin Falcon Chipset
This patch has been tested on a board similar to AMD Bettong.
00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus
Controller [1022:790b] (rev 4a)
00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC
Bridge [1022:790e] (rev 11)
root@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom
flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)
flashrom is free software, get the source code at
https://flashrom.org
Calibrating delay loop... OK.
coreboot table found at 0x9ffd6000.
Found chipset "AMD FP4".
Enabling flash write... OK.
Found Micron/Numonyx/ST flash chip "N25Q128..1E" (16384 kB, SPI)
mapped at physical address 0x00000000ff000000.
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
Original-Change-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d
Original-Reviewed-on: https://review.coreboot.org/21429
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Change-Id: I44e55fe9bdb5ac00ed118d1d3cdc2c80b5e997cf
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
---
M chipset_enable.c
M sb600spi.c
2 files changed, 24 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/21937/1
diff --git a/chipset_enable.c b/chipset_enable.c
index a3b7f8d..3437792 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1608,6 +1608,7 @@
{0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
{0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
{0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600},
+ {0x1022, 0x790e, OK, "AMD", "FP4", enable_flash_sb600},
{0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
{0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
{0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530},
diff --git a/sb600spi.c b/sb600spi.c
index 6bd5679..68f8d8a 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -149,6 +149,23 @@
"Please report this to flashrom@flashrom.org and include this log and\n"
"the output of lspci -nnvx, thanks!.\n", rev);
}
+ } else if (dev->device_id == 0x790e) {
+ struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x790B);
+ if (smbus_dev == NULL) {
+ msg_pdbg("No SMBus device with ID 1022:790B found.\n");
+ return;
+ }
+ uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID);
+ if (rev == 0x4a) {
+ amd_gen = CHIPSET_YANGTZE;
+ msg_pdbg("Yangtze detected.\n");
+ } else {
+ msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n"
+ "Please report this to flashrom@flashrom.org and include this log and\n"
+ "the output of lspci -nnvx, thanks!.\n", rev);
+ }
+
+
#endif
} else
msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n"
@@ -646,12 +663,13 @@
/* Look for the SMBus device. */
smbus_dev = pci_dev_find(0x1002, 0x4385);
- if (!smbus_dev) {
+ if (!smbus_dev)
smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */
- if (!smbus_dev) {
- msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
- return ERROR_NONFATAL;
- }
+ if (!smbus_dev)
+ smbus_dev = pci_dev_find(0x1022, 0x790b); /* AMD FP4 */
+ if (!smbus_dev) {
+ msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
+ return ERROR_NONFATAL;
}
/* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
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