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1 comment:
Patchset:
Have you tested that (and with that I mean that the *host* SCIP bit flips when the
CSE uses its own interface)?yes, I have verified by making CSE send a storage access command and read the SCIP from host side and host send a command and read the SCIP from CSE side. And there is no specific interface. It's same SPI controller MMIO offset bit 5 read in both cases.
Thanks, this is very valuable information! I knew that the CSE uses a similar
interface, but not that they (the host and the CSE interface) affect each other.
I just read the register description again and still can't find any clue about
that. Actually, the description when SCIP will be set looks like it would exclude
such a case, but it might also just be totally incomplete.While I pretty much expect such documentation and firmware issues, I have so
far mostly understood Intel's hardware design choices but I still can't understand
this one. Now I wonder even more how arbitration with other interfaces worked
(e.g. memory-mapped access, software sequencing) if at all.SW Sq is dropped in ADL so any access to SPI controller is via HW Sq.
Yes, but things have worked for 10y+ and I wonder how ;)
>
> Just to be sure, there's no chance that the CSE code is using the host interface
> instead of its own, right?No, they can't. CSE has access to SPI region as give via descriptor. And accessing the SPI controller just need to generate the HW seq from CSE side. CSE will have access to it's own region as specified in descriptor base/limit.
I'm not talking about flash regions. Um, you said "It's same SPI controller
MMIO offset..." but it's just the same register layout, right? Not the same
physical register?
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