Attention is currently required from: Bora Guvendik, Anil Kumar K, Nico Huber, Paul Menzel, Edward O'Callaghan, Anastasia Klimchuk.

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1 comment:

• File chipset_enable.c:

  • Patch Set #7, Line 2018:

    {0x8086, 0xa224, B_FS,   OK,  "Intel", "Lewisburg",			enable_flash_pch100},
    	{0x8086, 0x9da4, B_FS,   OK,  "Intel", "Cannonlake",			enable_flash_pch100},
    	{0x8086, 0x34a4, B_FS,   OK,  "Intel", "Icelake",			enable_flash_pch100},
    	{0x8086, 0x4da4, B_FS,   OK,  "Intel", "Jasperlake",			enable_flash_pch100},
    	{0x8086, 0xa0a4, B_FS,   OK,  "Intel", "Tigerlake",			enable_flash_pch100},
    	{0x8086, 0x7aa4, B_FS,   OK,  "Intel", "Alderlake-S",			enable_flash_pch100},
    	{0x8086, 0x51a4, B_FS,   OK,  "Intel", "Alderlake-P / M",	        enable_flash_pch100},
    

    flashrom uses LPC/eSPI PCI IDs instead of SPI PCI IDs. The SPI PCI device is not always visible, and didn't exist before Sunrise Point. Adding these IDs will result in flashrom complaining about "unexpected second chipset match" in several cases, which is undesired.

    Note that Intel PCHs are never marked as `OK`, but `DEP` (config DEPendent) instead. This is because IFD/ME can prevent successful flashing in some cases: IFD can restrict region access, reflashing the ME region while the ME is active often ends up badly (data corruption).

    `B_FS` indicates that these chipsets support SPI and FWH. I'd say `B_S` is the correct choice.

    Also, none of these chipsets should use the `enable_flash_pch100` function. Upstream flashrom differentiates between PCH generations (there's some differences w.r.t. protected range registers and IFD regions).

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