Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen.

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2 comments:

• File ichspi.c:

  • Patch Set #1, Line 1848: case CHIPSET_METEOR_LAKE:

    this might increase the maintenance burden going forward ? for example: we need to add PTL, WCL etc. etc. platform going forward.

    can we add `CHIPSET_METEOR_LAKE` as last entry for now inside `ich_chipset` and then update this logic something like this:

    ```
    if (ich_generation >= CHIPSET_METEOR_LAKE) {

              /*
    		 * Starting from Meteor Lake, we need to fetch the region
    		 * read/write access permissions from the BIOS_BM registers
    		 * because we need to support FREG9 or above.
    		 */
    		*region_read_access = mmio_readw(ich_spibar + ICH_REG_BIOS_BM_RAP);
    		*region_write_access = mmio_readw(ich_spibar + ICH_REG_BIOS_BM_WAP);
    } else {

    /*
    		 * FRAP - Flash Regions Access Permissions Register
    		 * Bit Descriptions:
    		 * 31:24 BIOS Master Write Access Grant (BMWAG)
    		 * 23:16 BIOS Master Read Access Grant (BMRAG)
    		 * 15:8 BIOS Region Write Access (BRWA)
    		 * 7:0 BIOS Region Read Access (BRRA)
    		 */
    		tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
    		msg_pdbg("0x50: 0x%08"PRIx32" (FRAP)\n", tmp);
    		msg_pdbg("BMWAG 0x%02"PRIx32", ", ICH_BMWAG(tmp));
    		msg_pdbg("BMRAG 0x%02"PRIx32", ", ICH_BMRAG(tmp));
    		msg_pdbg("BRWA 0x%02"PRIx32", ", ICH_BRWA(tmp));
    		msg_pdbg("BRRA 0x%02"PRIx32"\n", ICH_BRRA(tmp));

    		*region_read_access = ICH_BRRA(tmp);
    		*region_write_access = ICH_BRWA(tmp);
    }

    ```

  • Patch Set #1, Line 2236: ich9_handle_frap

    isn't `ich9_handle_frap` function takes only takes 3 arguments ?

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