Edward O'Callaghan has uploaded this change for review.

View Change

ichspi.c: Mostly remove ichspi_lock from global scope

WIP, maybe go all the way.

Change-Id: Ie5b170b1a3a3f417527f4dfbe4755e00edeadf1e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M ichspi.c
1 file changed, 26 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/69515/1

diff --git a/ichspi.c b/ichspi.c
index 4e982f0..9196112 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -256,7 +256,7 @@
 };
 
 /* ICH SPI configuration lock-down. May be set during chipset enabling. */
-static bool ichspi_lock = false;
+static bool g_ichspi_lock;
 
 static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
 static uint32_t ichspi_bbar;
@@ -782,7 +782,7 @@
  *
  * It should be called before ICH sends any spi command.
  */
-static int ich_init_opcodes(enum ich_chipset ich_gen)
+static int ich_init_opcodes(enum ich_chipset ich_gen, bool ichspi_lock)
 {
 	int rc = 0;
 	OPCODES *curopcodes_done;
@@ -1142,7 +1142,7 @@
 	/* find cmd in opcodes-table */
 	opcode_index = find_opcode(curopcodes, cmd);
 	if (opcode_index == -1) {
-		if (!ichspi_lock)
+		if (!g_ichspi_lock)
 			opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
 		if (opcode_index == SPI_INVALID_LENGTH) {
 			msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
@@ -1628,7 +1628,7 @@
 				 * during execution of the next command anyway.
 				 * No need to bother with fixups.
 				 */
-				if (!ichspi_lock) {
+				if (!g_ichspi_lock) {
 					oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
 					if (oppos == -1)
 						continue;
@@ -1816,6 +1816,7 @@
 static int init_ich7_spi(void *spibar, enum ich_chipset ich_gen)
 {
 	unsigned int i;
+	bool ichspi_lock = false;
 
 	msg_pdbg("0x00: 0x%04x     (SPIS)\n",	mmio_readw(spibar + 0));
 	msg_pdbg("0x02: 0x%04x     (SPIC)\n",	mmio_readw(spibar + 2));
@@ -1838,8 +1839,9 @@
 		msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
 		ichspi_lock = true;
 	}
-	ich_init_opcodes(ich_gen);
+	ich_init_opcodes(ich_gen, ichspi_lock);
 	ich_set_bbar(0, ich_gen);
+	g_ichspi_lock = ichspi_lock;
 	register_spi_master(&spi_master_ich7, NULL);
 
 	return 0;
@@ -1953,6 +1955,7 @@
 	struct ich_descriptors desc = { 0 };
 	enum ich_spi_mode ich_spi_mode = ich_auto;
 	size_t num_freg, num_pr, reg_pr0;
+	bool ichspi_lock = false;
 
 	struct hwseq_data hwseq_data;
 	init_chipset_properties(&swseq_data, &hwseq_data, &num_freg, &num_pr, &reg_pr0, ich_gen);
@@ -1974,7 +1977,7 @@
 		msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
 			  "the Master Section of the flash descriptor are NOT in effect. Please note\n"
 			  "that Protected Range (PR) restrictions still apply.\n");
-	ich_init_opcodes(ich_gen);
+	ich_init_opcodes(ich_gen, ichspi_lock);
 
 	if (desc_valid) {
 		tmp2 = mmio_readw(spibar + ICH9_REG_HSFC);
@@ -2163,6 +2166,8 @@
 		ich_spi_mode = ich_hwseq;
 	}
 
+	g_ichspi_lock = ichspi_lock;
+
 	if (ich_spi_mode == ich_hwseq) {
 		if (!desc_valid) {
 			msg_perr("Hardware sequencing was requested "
@@ -2228,6 +2233,7 @@
 int via_init_spi(uint32_t mmio_base)
 {
 	int i;
+	bool ichspi_lock = false;
 
 	ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
 	if (ich_spibar == ERROR_PTR)
@@ -2268,7 +2274,8 @@
 	}
 
 	ich_set_bbar(0, ich_generation);
-	ich_init_opcodes(ich_generation);
+	ich_init_opcodes(ich_generation, ichspi_lock);
+	g_ichspi_lock = ichspi_lock;
 
 	return 0;
 }

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