Nico Huber merged this change.
chipset_enable: Add Apollo Lake
It works the same as 100 series PCHs and on. The SPI device is at
0:0d.2, though. Mark as BAD until `ichspi` is revised.
Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
M chipset_enable.c
M programmer.h
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/chipset_enable.c b/chipset_enable.c
index 89458c6..24ac64a 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -598,6 +598,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_APOLLO_LAKE:
reg_name = "BIOS_SPI_BC";
gcs = pci_read_long(dev, 0xdc);
bild = (gcs >> 7) & 1;
@@ -649,6 +650,9 @@
static const struct boot_straps boot_straps_pch8_lp[] =
{ { "SPI", BUS_SPI },
{ "LPC", BUS_LPC | BUS_FWH } };
+ static const struct boot_straps boot_straps_apl[] =
+ { { "SPI", BUS_SPI },
+ { "reserved" } };
static const struct boot_straps boot_straps_unknown[] =
{ { "unknown" },
{ "unknown" },
@@ -690,6 +694,9 @@
case CHIPSET_C620_SERIES_LEWISBURG:
boot_straps = boot_straps_pch8_lp;
break;
+ case CHIPSET_APOLLO_LAKE:
+ boot_straps = boot_straps_apl;
+ break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
boot_straps = boot_straps_unknown;
@@ -712,6 +719,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_APOLLO_LAKE:
bbs = (gcs >> 6) & 0x1;
break;
default:
@@ -866,7 +874,9 @@
return 0;
}
-static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation)
+static int enable_flash_pch100_or_c620(
+ struct pci_dev *const dev, const char *const name,
+ const int slot, const int func, const enum ich_chipset pch_generation)
{
int ret = ERROR_FATAL;
@@ -887,7 +897,7 @@
pci_init(pci_acc);
register_shutdown(enable_flash_pch100_shutdown, pci_acc);
- struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5);
+ struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func);
if (!spi_dev) {
msg_perr("Can't allocate PCI device.\n");
return ret;
@@ -929,12 +939,17 @@
static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
{
- return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT);
+ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT);
}
static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
{
- return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG);
+ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
+}
+
+static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
+{
+ return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
}
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
@@ -2011,6 +2026,7 @@
{0x8086, 0xa2c8, B_S, NT, "Intel", "B250", enable_flash_pch100},
{0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100},
{0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
+ {0x8086, 0x5ae8, B_S, BAD, "Intel", "Apollo Lake", enable_flash_apl},
#endif
{0},
};
diff --git a/programmer.h b/programmer.h
index e342898..f4e8b46 100644
--- a/programmer.h
+++ b/programmer.h
@@ -626,6 +626,7 @@
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG,
+ CHIPSET_APOLLO_LAKE,
};
/* ichspi.c */
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