ChrisEric1 CECL has uploaded this change for review.
Add support for AMD Ryzen flashing
Tested AMD Ryzen Support on HP Pavilion 590-p0077c,
I am able to flash using F.15 or older,
but I can downgrade if a newer Firmware
is installed using afuwinx64 which is a vendor tool
This is due to flashrom SPI lockdown on newer firmwares by HP.
It seems HP UEFI Diags uses AFU Flash embedded in.
It also comes with a AMD Ryzen 3 2200G with 16MB,
so it may not work with chips more that 16MB,
it is currently untested by me,
since this is the only AMD PC I own.
Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0
Signed-off-by: Christopher Lentocha <christopherericlentocha@gmail.com>
---
M chipset_enable.c
M flashchips.c
M include/flashchips.h
M include/programmer.h
M sb600spi.c
M spi25.c
6 files changed, 139 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/58/72058/1
diff --git a/chipset_enable.c b/chipset_enable.c
index b9144d1..90fa522 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1772,7 +1772,7 @@
{0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
{0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
{0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600},
- {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600},
+ {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4/FP5/AM4", enable_flash_sb600},
{0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501},
{0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496},
{0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530},
diff --git a/flashchips.c b/flashchips.c
index 625fe62..cbb6e5e 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6384,6 +6384,45 @@
{
.vendor = "GigaDevice",
+ .name = "GD25LQ256",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25LQ256,
+ .total_size = 32768,
+ .page_size = 256,
+ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
+ .tested = TEST_UNTESTED,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp4_srwd,
+ .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {1695, 2000},
+ },
+
+ {
+ .vendor = "GigaDevice",
.name = "GD25B128B/GD25Q128B",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
@@ -17893,6 +17932,53 @@
{
.vendor = "Winbond",
+ .name = "W25Q256JW",
+ .bustype = BUS_SPI,
+ .manufacture_id = WINBOND_NEX_ID,
+ .model_id = WINBOND_NEX_W25Q256JW,
+ .total_size = 32768,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
+ /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */
+ .unlock = spi_disable_blockprotect,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {1700, 1950},
+ },
+
+ {
+ .vendor = "Winbond",
.name = "W25Q256FV",
.bustype = BUS_SPI,
.manufacture_id = WINBOND_NEX_ID,
diff --git a/include/flashchips.h b/include/flashchips.h
index 5df42dc..c5f7f37 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -400,6 +400,7 @@
#define GIGADEVICE_GD25LQ32 0x6016
#define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */
#define GIGADEVICE_GD25LQ128CD 0x6018
+#define GIGADEVICE_GD25LQ256 0x6019
#define GIGADEVICE_GD25WQ80E 0x6514
#define GIGADEVICE_GD29GL064CAB 0x7E0601
@@ -977,6 +978,7 @@
#define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */
#define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */
#define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */
+#define WINBOND_NEX_W25Q256JW 0x6019 /* W25Q256JW */
#define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */
#define WINBOND_NEX_W25Q64JV 0x7017 /* W25Q64JV */
#define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */
diff --git a/include/programmer.h b/include/programmer.h
index 9e706d5..1150daf 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -25,6 +25,8 @@
#include "flash.h" /* for chipaddr and flashctx */
+extern uint8_t RZN32BM;
+
enum programmer_type {
PCI = 1, /* to detect uninitialized values */
USB,
diff --git a/sb600spi.c b/sb600spi.c
index 5b9ac45..4c287b7 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -53,6 +53,7 @@
#define FIFO_SIZE_OLD 8
#define FIFO_SIZE_YANGTZE 71
+uint8_t RZN32BM = 0;
#define SPI100_CMD_CODE_REG 0x45
#define SPI100_CMD_TRIGGER_REG 0x47
@@ -124,6 +125,11 @@
if (rev == 0x4a) {
msg_pdbg("Yangtze detected.\n");
return CHIPSET_YANGTZE;
+ } else if (rev == 0x51 || rev == 0x59 || rev == 0x61) {
+ //RZN32BM = mmio_readb(sb600_spibar + 0x50) & 0x1;
+ //amd_gen = CHIPSET_YANGTZE;
+ msg_pdbg("Ryzen detected.\n");
+ return CHIPSET_YANGTZE;
/**
* FCH chipsets called 'Promontory' are one's with the
* so-called SPI100 ip core that uses memory mapping and
@@ -513,7 +519,14 @@
tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3;
msg_pdbg("NormSpeed is %s\n", spispeeds[tmp]);
if (spispeed_idx < 0) {
- spispeed_idx = 3; /* Default to 16.5 MHz */
+ if (amd_gen >= CHIPSET_YANGTZE)
+ {
+ spispeed_idx = 1; /* Default to 33.3 MHz */
+ }
+ else
+ {
+ spispeed_idx = 3; /* Default to 16.5 MHz */
+ }
}
}
if (spispeed_idx < 0) {
diff --git a/spi25.c b/spi25.c
index f54e4c8..25b5bcb 100644
--- a/spi25.c
+++ b/spi25.c
@@ -393,7 +393,10 @@
const bool native_4ba, const unsigned int addr)
{
if (native_4ba || flash->in_4ba_mode) {
- if (!spi_master_4ba(flash)) {
+ if (!spi_master_4ba(flash) && RZN32BM != 1) {
+ msg_cwarn("4-byte address requested but master can't handle 4-byte addresses.\n");
+ return -1;
+ } else if (!spi_master_4ba(flash)) {
msg_cwarn("4-byte address requested but master can't handle 4-byte addresses.\n");
return -1;
}
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