Nico Huber posted comments on this change.

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Patch set 5:

(1 comment)

• File spi25.c:

  • Patch Set #5, Line 380: "Please report a bug at flashrom@flashrom.org\n");

    How so? If you're referring to chip erase commands, those are handled using

    I'm talking about the block erase commands. If the core read/erase/write
    code tries a native 4BA erase and the master doesn't support it, we end
    up here.

    Maybe we should handle native 4BA erase commands differently. e.g. put
    them in a separate list? or bail out earlier? Though, my last plan was
    to ask the master anyway if an erase command is supported (e.g. 3BA
    commands may not be as well in case of locked opcodes on Intel) instead
    of going through all the preparations and trying.

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