Attention is currently required from: Subrata Banik, Caveh Jalali, Rizwan Qureshi, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Angel Pons, Nick Vaccaro, Alex Levin, YH Lin, Boris Mittelberg.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
In regards to H_SCIP. The recommendation is to check this bit before starting a transaction. This indicates a transaction by the same master and not the transactions being served for other masters.
Thank you Rizwan. That's how I always understood it. However, Subrata's test
result suggest otherwise:
Have you tested that (and with that I mean that the *host* SCIP bit flips when the
CSE uses its own interface)?
yes, I have verified by making CSE send a storage access command and read the SCIP from host side and host send a command and read the SCIP from CSE side. And there is no specific interface. It's same SPI controller MMIO offset bit 5 read in both cases.
This leaves some questions. Is something broken wrt. arbitration? How does
arbitration work if two masters set FGO at the same time? is that accounted
for in the hardware?
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