Attention is currently required from: Edward O'Callaghan.

Edward O'Callaghan uploaded patch set #2 to this change.

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intel: Add Alder Lake support [WIP]

Get this moving for Intel.

BUG=b:XXX
TEST=<none>

Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 31 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/62251/2

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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Gerrit-Change-Number: 62251
Gerrit-PatchSet: 2
Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-Attention: Edward O'Callaghan <quasisec@chromium.org>
Gerrit-MessageType: newpatchset