Attention is currently required from: Sam McNally, Edward O'Callaghan, Angel Pons.
Nico Huber would like Sam McNally, build bot (Jenkins), Edward O'Callaghan and Angel Pons to review this change.
chipset_enable.c: check return value from rphysmap() call
Port from the ChromiumOS fork of flashrom.
Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
M chipset_enable.c
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/67852/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 6280876..6f75d66 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -930,6 +930,8 @@
uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
+ if (spibar == ERROR_PTR)
+ return ERROR_FATAL;
/* Enable Flash Writes.
* Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
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