Anastasia Klimchuk submitted this change.
ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros
This patch renames the `WET` macro definitions based on its
availability with PCH100 onwards chipset.
HSFC_WET_OFF -> PCH100_HSFC_WET_OFF
HSFC_WET -> PCH100_HSFC_WET
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
M ichspi.c
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ichspi.c b/ichspi.c
index 5d4d4d7..36ee3b9 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -49,8 +49,8 @@
#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
/* New HSFC Control bit */
-#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
-#define HSFC_WET (0x1 << HSFC_WET_OFF)
+#define PCH100_HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
+#define PCH100_HSFC_WET (0x1 << PCH100_HSFC_WET_OFF)
#define PCH100_FADDR_FLA 0x07ffffff
@@ -464,7 +464,7 @@
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_ELKHART_LAKE:
_pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
- pprint_reg(HSFC, WET, reg_val, ", ");
+ pprint_reg(PCH100_HSFC, WET, reg_val, ", ");
break;
default:
pprint_reg(HSFC, FCYCLE, reg_val, ", ");
To view, visit change 62888. To unsubscribe, or for help writing mail filters, visit settings.