Attention is currently required from: Nicholas Chin, ZhiYuanNJ.

ZhiYuanNJ uploaded patch set #3 to this change.

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ch347_spi: Add spi clock frequency selection

CH347 SPI interface supports up to 60M.
For example, to set a 30M spi rate, use - p ch347_spi:spispeed=30M.

Change-Id: If2be48929db540a6598ac0b60b37e64597156db7
Signed-off-by: ZhiYuanNJ Liu <871238103@qq.com>
---
M ch347_spi.c
1 file changed, 37 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/82776/3

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