Edward O'Callaghan has uploaded this change for review.
chipset_enable.c: Add Apollolake and Geminilake support
Adds product id's:
0x5af0 for Apollolake and 0x31f0 for Geminilake.
Currently, on Apollolake platform, the SPI PCI device is hidden in
the OS. Thus, flashrom is not able to find the SPI device while
walking the PCI tree. Instead use the PCI ID of APL host bridge. In
the callback for enabling APL flash, use mmio-based access to mmap
SPI PCI device and work with it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I533a426bbf8e9c5efef0cf693693086e8efc1f57
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M chipset_enable.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/47091/1
diff --git a/chipset_enable.c b/chipset_enable.c
index c664918..01d0291 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1896,6 +1896,7 @@
{0x8086, 0x2917, B_FS, DEP, "Intel", "ICH9M-E", enable_flash_ich9},
{0x8086, 0x2918, B_FS, DEP, "Intel", "ICH9", enable_flash_ich9},
{0x8086, 0x2919, B_FS, DEP, "Intel", "ICH9M", enable_flash_ich9},
+ {0x8086, 0x31f0, B_FS, OK, "Intel", "Geminilake", enable_flash_apl},
{0x8086, 0x3a10, B_FS, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10},
{0x8086, 0x3a14, B_FS, DEP, "Intel", "ICH10DO", enable_flash_ich10},
{0x8086, 0x3a16, B_FS, DEP, "Intel", "ICH10R", enable_flash_ich10},
@@ -1920,6 +1921,7 @@
{0x8086, 0x3b16, B_FS, NT, "Intel", "3450", enable_flash_pch5},
{0x8086, 0x3b1e, B_FS, NT, "Intel", "B55", enable_flash_pch5},
{0x8086, 0x5031, B_FS, OK, "Intel", "EP80579", enable_flash_ich7},
+ {0x8086, 0x5af0, B_FS, OK, "Intel", "Apollolake", enable_flash_apl},
{0x8086, 0x7000, B_P, OK, "Intel", "PIIX3", enable_flash_piix4},
{0x8086, 0x7110, B_P, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
{0x8086, 0x7198, B_P, OK, "Intel", "440MX", enable_flash_piix4},
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