Edward O'Callaghan has uploaded this change for review.

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ichspi.c: plumb flashctx though hwseq xfer helper

Change is a NOP to prepare ichspi to remove hwseq_data being
a global symbol. This allows for the helper functions to derive
their data from the driver data context.

Change-Id: I67b5aa6350930d912e5036473ac3e792debac0bd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M ichspi.c
1 file changed, 23 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/68772/1

diff --git a/ichspi.c b/ichspi.c
index 6d3535c..5d9fe0c 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1345,7 +1345,8 @@
 }
 
 /* Fire up a transfer using the hardware sequencer. */
-static void ich_start_hwseq_xfer(uint32_t hsfc_cycle, uint32_t flash_addr, size_t len,
+static void ich_start_hwseq_xfer(const struct flashctx *flash,
+		uint32_t hsfc_cycle, uint32_t flash_addr, size_t len,
 		uint32_t addr_mask)
 {
 	uint16_t hsfc;
@@ -1376,7 +1377,7 @@
 }
 
 /* Execute SPI flash transfer */
-static int ich_exec_sync_hwseq_xfer(uint32_t hsfc_cycle, uint32_t flash_addr,
+static int ich_exec_sync_hwseq_xfer(const struct flashctx *flash, uint32_t hsfc_cycle, uint32_t flash_addr,
 				size_t len, enum ich_chipset ich_gen, uint32_t addr_mask)
 {
 	if (ich_wait_for_hwseq_spi_cycle_complete()) {
@@ -1384,7 +1385,7 @@
 		return 1;
 	}
 
-	ich_start_hwseq_xfer(hsfc_cycle, flash_addr, len, addr_mask);
+	ich_start_hwseq_xfer(flash, hsfc_cycle, flash_addr, len, addr_mask);
 	return ich_hwseq_wait_for_cycle_complete(len, ich_gen, addr_mask);
 }
 
@@ -1399,7 +1400,7 @@
 	}
 	msg_pdbg("Reading Status register\n");
 
-	if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_RD_STATUS, 0, len, ich_generation,
+	if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation,
 		hwseq_data->addr_mask)) {
 		msg_perr("Reading Status register failed\n!!");
 		return -1;
@@ -1422,7 +1423,7 @@
 
 	ich_fill_data(&value, len, ICH9_REG_FDATA0);
 
-	if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_WR_STATUS, 0, len, ich_generation,
+	if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation,
 		hwseq_data->addr_mask)) {
 		msg_perr("Writing Status register failed\n!!");
 		return -1;
@@ -1518,7 +1519,7 @@
 
 	msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
 
-	if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation,
+	if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation,
 		hwseq_data->addr_mask))
 		return -1;
 	return 0;
@@ -1546,7 +1547,7 @@
 		/* as well as flash chip page borders as demanded in the Intel datasheets. */
 		block_len = min(block_len, 256 - (addr & 0xFF));
 
-		if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_READ, addr, block_len, ich_generation,
+		if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_READ, addr, block_len, ich_generation,
 			hwseq_data->addr_mask))
 			return 1;
 		ich_read_data(buf, block_len, ICH9_REG_FDATA0);
@@ -1579,7 +1580,7 @@
 		block_len = min(block_len, 256 - (addr & 0xFF));
 		ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
 
-		if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_WRITE, addr, block_len, ich_generation,
+		if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WRITE, addr, block_len, ich_generation,
 			hwseq_data->addr_mask))
 			return -1;
 		addr += block_len;

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