Edward O'Callaghan submitted this change.
writeprotect.c: refactor and fix wp_mode functions
This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.
Use a lookup table in get_wp_mode() and drop the srp_bit_present check,
since a chip without SRP is just FLASHROM_WP_MODE_DISABLED.
Add a srp_bit_present check to set_wp_mode() if the mode requires it.
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,status} on AMD dut
Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
---
M writeprotect.c
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/writeprotect.c b/writeprotect.c
index 6b3bbcf..5893593 100644
--- a/writeprotect.c
+++ b/writeprotect.c
@@ -351,16 +351,17 @@
/** Get the mode selected by a WP configuration. */
static int get_wp_mode(enum flashrom_wp_mode *mode, const struct wp_bits *bits)
{
- if (!bits->srp_bit_present)
- return FLASHROM_WP_ERR_CHIP_UNSUPPORTED;
+ const enum flashrom_wp_mode wp_modes[2][2] = {
+ {
+ FLASHROM_WP_MODE_DISABLED, /* srl=0, srp=0 */
+ FLASHROM_WP_MODE_HARDWARE, /* srl=0, srp=1 */
+ }, {
+ FLASHROM_WP_MODE_POWER_CYCLE, /* srl=1, srp=0 */
+ FLASHROM_WP_MODE_PERMANENT, /* srl=1, srp=1 */
+ },
+ };
- if (bits->srl_bit_present && bits->srl == 1) {
- *mode = bits->srp ? FLASHROM_WP_MODE_PERMANENT :
- FLASHROM_WP_MODE_POWER_CYCLE;
- } else {
- *mode = bits->srp ? FLASHROM_WP_MODE_HARDWARE :
- FLASHROM_WP_MODE_DISABLED;
- }
+ *mode = wp_modes[bits->srl][bits->srp];
return FLASHROM_WP_OK;
}
@@ -375,6 +376,9 @@
return FLASHROM_WP_OK;
case FLASHROM_WP_MODE_HARDWARE:
+ if (!bits->srp_bit_present)
+ return FLASHROM_WP_ERR_CHIP_UNSUPPORTED;
+
bits->srl = 0;
bits->srp = 1;
return FLASHROM_WP_OK;
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