Edward O'Callaghan submitted this change.
ft2232_spi: Fix broken GPIOL cs_bits state (#126)
This only sets 3rd CS# bit be asserted during read/write operations.
Tested and confirmed working on 4232H & PicoTap ft2232 programmers
against MX25R6435F & S25FL128S chips.
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
---
M ft2232_spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 3e4dc9e..1a5b2fe 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -495,7 +495,7 @@
*/
msg_pspew("Assert CS#\n");
buf[i++] = SET_BITS_LOW;
- buf[i++] = 0 & ~cs_bits; /* assertive */
+ buf[i++] = ~ 0x08 & cs_bits; /* assert CS (3rd) bit only */
buf[i++] = pindir;
if (writecnt) {
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