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1 comment:
Patchset:
Have you tested that (and with that I mean that the *host* SCIP bit flips when the
CSE uses its own interface)?yes, I have verified by making CSE send a storage access command and read the SCIP from host side and host send a command and read the SCIP from CSE side. And there is no specific interface. It's same SPI controller MMIO offset bit 5 read in both cases.
Thanks, this is very valuable information! I knew that the CSE uses a similar
interface, but not that they (the host and the CSE interface) affect each other.
I just read the register description again and still can't find any clue about
that. Actually, the description when SCIP will be set looks like it would exclude
such a case, but it might also just be totally incomplete.While I pretty much expect such documentation and firmware issues, I have so
far mostly understood Intel's hardware design choices but I still can't understand
this one. Now I wonder even more how arbitration with other interfaces worked
(e.g. memory-mapped access, software sequencing) if at all.SW Sq is dropped in ADL so any access to SPI controller is via HW Sq.
Yes, but things have worked for 10y+ and I wonder how ;)
Some feature that CSE enables with ADL need sporadic access to CSE RW region. hence, as per CSE team's data, this is expected.
So was everything synchronized before? e.g. applications like AMT didn't need
to access flash? How did it work when a non-volatile variable was updated?
Sorry, my head is full of questions now. Also, when the CSE is booting up,
when does it stop reading from flash? I would have guessed that it doesn't
have enough SRAM to read everything before system DRAM is up and when system
DRAM is up, coreboot already wants to write to flash (e.g. training params
in "MRC cache").
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