Edward O'Callaghan has uploaded this change for review.
flashrom,internal: Move board_cfg up in the CFG to prog_init
Avoid the need for a copy of the programmer_cfg within the
internal programmer. Move the board_cfg up into programmer_init().
TEST=`$ ./flashrom -p internal --flash-name`.
Change-Id: I30bc4eefeb589d3ee7827fcfea81985292c88a10
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M flashrom.c
M internal.c
2 files changed, 29 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/73492/1
diff --git a/flashrom.c b/flashrom.c
index da46354..f2ee3a9 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -144,7 +144,8 @@
/* Default to allowing writes. Broken programmers set this to 0. */
programmer_may_write = true;
- struct programmer_cfg cfg;
+ struct board_cfg bcfg = {0};
+ struct programmer_cfg cfg = { .bcfg = &bcfg };
if (param) {
cfg.params = strdup(param);
diff --git a/internal.c b/internal.c
index bba7043..f2fff0d 100644
--- a/internal.c
+++ b/internal.c
@@ -149,7 +149,6 @@
const char *cb_model = NULL;
#endif
bool force_boardenable = false;
- struct board_cfg bcfg = {0};
ret = get_params(cfg,
&force_boardenable, &force_boardmismatch,
@@ -162,7 +161,7 @@
* is found, the host controller init routine sets the
* internal_buses_supported bitfield.
*/
- bcfg.internal_buses_supported = BUS_NONSPI;
+ cfg->bcfg->internal_buses_supported = BUS_NONSPI;
if (try_mtd(cfg) == 0) {
ret = 0;
@@ -201,12 +200,12 @@
}
}
- bcfg.is_laptop = 2; /* Assume that we don't know by default. */
+ cfg->bcfg->is_laptop = 2; /* Assume that we don't know by default. */
- dmi_init(&bcfg.is_laptop);
+ dmi_init(&(cfg->bcfg->is_laptop));
/* In case Super I/O probing would cause pretty explosions. */
- board_handle_before_superio(&bcfg, force_boardenable);
+ board_handle_before_superio(cfg->bcfg, force_boardenable);
/* Probe for the Super I/O chip and fill global struct superio. */
probe_superio();
@@ -219,22 +218,21 @@
#endif
/* Check laptop whitelist. */
- board_handle_before_laptop(&bcfg, force_boardenable);
+ board_handle_before_laptop(cfg->bcfg, force_boardenable);
/*
* Disable all internal buses by default if we are not sure
* this isn't a laptop. Board-enables may override this,
* non-legacy buses (SPI and opaque atm) are probed anyway.
*/
- if (bcfg.is_laptop && !(bcfg.laptop_ok || force_laptop || (not_a_laptop && bcfg.is_laptop == 2)))
- bcfg.internal_buses_supported = BUS_NONE;
+ if (cfg->bcfg->is_laptop && !(cfg->bcfg->laptop_ok ||
+ force_laptop || (not_a_laptop && cfg->bcfg->is_laptop == 2)))
+ cfg->bcfg->internal_buses_supported = BUS_NONE;
/* try to enable it. Failure IS an option, since not all motherboards
* really need this to be done, etc., etc.
*/
- struct programmer_cfg icfg = *cfg;
- icfg.bcfg = &bcfg;
- ret = chipset_flash_enable(&icfg);
+ ret = chipset_flash_enable(cfg);
if (ret == -2) {
msg_perr("WARNING: No chipset found. Flash detection "
"will most likely fail.\n");
@@ -247,7 +245,7 @@
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
init_superio_ite(cfg);
- if (board_flash_enable(&bcfg,
+ if (board_flash_enable(cfg->bcfg,
board_vendor, board_model, cb_vendor, cb_model, force_boardenable)) {
msg_perr("Aborting to be safe.\n");
ret = 1;
@@ -255,10 +253,10 @@
}
#endif
- internal_par_init(bcfg.internal_buses_supported);
+ internal_par_init(cfg->bcfg->internal_buses_supported);
/* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */
- report_nonwl_laptop_detected(&bcfg);
+ report_nonwl_laptop_detected(cfg->bcfg);
ret = 0;
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