Sergii Dmytruk has uploaded this change for review.
spi25_statusreg: make "configuration registers" an alias to SRs
Sometimes it's only a matter of naming and these behave exactly like
SR2/SR3 (Spansion S25FL256L and S25FL128L), so they can be treated as a
variation on status registers.
Change-Id: I27e89626037dcb0ed078029efe1e919b1f3e88fe
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
M flashchips.c
M include/flash.h
M spi25_statusreg.c
3 files changed, 51 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/69399/1
diff --git a/flashchips.c b/flashchips.c
index 69e524f..3ba07a3 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -9365,7 +9365,7 @@
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
- .tb = {CONFIG, 3, OTP},
+ .tb = {CONFIG1, 3, OTP},
.wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
},
.decode_range = DECODE_RANGE_SPI25,
@@ -9413,7 +9413,7 @@
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
- .tb = {CONFIG, 3, OTP},
+ .tb = {CONFIG1, 3, OTP},
},
.decode_range = DECODE_RANGE_SPI25,
},
@@ -16467,6 +16467,13 @@
.total_size = 16384,
.page_size = 256,
/* 4 x 256B Security Region (OTP) */
+ /*
+ * Note: Map of registers names:
+ * STATUS1 ... Status Register 1
+ * ... Status Register 2 (read-only)
+ * STATUS2/CONFIG1 ... Configuration Register 1
+ * STATUS3/CONFIG2 ... Configuration Register 2
+ */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP,
.tested = TEST_UNTESTED,
.probe = PROBE_SPI_RDID,
@@ -16497,20 +16504,13 @@
.voltage = {2700, 3600},
.reg_bits =
{
- /*
- * Note: This chip has a read-only Status Register 2 that is not
- * counted here. Registers are mapped as follows:
- * STATUS1 ... Status Register 1
- * STATUS2 ... Configuration Register 1
- * STATUS3 ... Configuration Register 2
- */
.srp = {STATUS1, 7, RW},
- .srl = {STATUS2, 0, RW},
+ .srl = {CONFIG1, 0, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.tb = {STATUS1, 5, RW},
.sec = {STATUS1, 6, RW},
- .cmp = {STATUS2, 6, RW},
- .wps = {STATUS3, 2, RW},
+ .cmp = {CONFIG1, 6, RW},
+ .wps = {CONFIG2, 2, RW},
},
.decode_range = DECODE_RANGE_SPI25,
},
@@ -16951,6 +16951,13 @@
.total_size = 32768,
.page_size = 256,
/* 4 x 256B Security Region (OTP) */
+ /*
+ * Note: Map of registers names:
+ * STATUS1 ... Status Register 1
+ * ... Status Register 2 (read-only)
+ * STATUS2/CONFIG1 ... Configuration Register 1
+ * STATUS3/CONFIG2 ... Configuration Register 2
+ */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP |
FEATURE_4BA_ENTER | FEATURE_4BA_NATIVE,
.tested = TEST_UNTESTED,
@@ -16991,19 +16998,12 @@
.voltage = {2700, 3600},
.reg_bits =
{
- /*
- * Note: This chip has a read-only Status Register 2 that is not
- * counted here. Registers are mapped as follows:
- * STATUS1 ... Status Register 1
- * STATUS2 ... Configuration Register 1
- * STATUS3 ... Configuration Register 2
- */
.srp = {STATUS1, 7, RW},
- .srl = {STATUS2, 0, RW},
+ .srl = {CONFIG1, 0, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.tb = {STATUS1, 6, RW},
- .cmp = {STATUS2, 6, RW},
- .wps = {STATUS3, 2, RW},
+ .cmp = {CONFIG1, 6, RW},
+ .wps = {CONFIG2, 2, RW},
},
.decode_range = DECODE_RANGE_SPI25,
},
diff --git a/include/flash.h b/include/flash.h
index d18e25e..0a1fe02 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -161,8 +161,11 @@
*/
#define FEATURE_SCUR (1 << 24)
-/* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */
-#define FEATURE_CFGR (1 << 25)
+/*
+ * Some chips read SR2 with 0x15 opcode and call it "configuration register".
+ * Writes are done as for FEATURE_WRSR_EXT2.
+ */
+#define FEATURE_RDSR2_0x15 ((1 << 25) | FEATURE_WRSR_EXT2)
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
@@ -192,13 +195,17 @@
#define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurrences. */
typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
+/* For chips that call SR2 "Configuration Register 1" */
+#define CONFIG1 STATUS2
+/* For chips that call SR3 "Configuration Register 2" */
+#define CONFIG2 STATUS3
+
enum flash_reg {
INVALID_REG = 0,
STATUS1,
STATUS2,
STATUS3,
SECURITY,
- CONFIG,
MAX_REGISTERS
};
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index b178b2e..d90ff26 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -107,23 +107,6 @@
*/
msg_cerr("Cannot write SECURITY: unsupported by design\n");
return 1;
- case CONFIG:
- /*
- * This one is read via a separate command, but written as if it's SR2
- * in FEATURE_WRSR_EXT2 case of WRSR command.
- */
- if (feature_bits & FEATURE_CFGR) {
- write_cmd[0] = JEDEC_WRSR;
- if (spi_read_register(flash, STATUS1, &write_cmd[1])) {
- msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n");
- return 1;
- }
- write_cmd[2] = value;
- write_cmd_len = 3;
- break;
- }
- msg_cerr("Cannot write CONFIG: unsupported by chip\n");
- return 1;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@@ -205,6 +188,11 @@
read_cmd = JEDEC_RDSR;
break;
case STATUS2:
+ /* This check must go first because FEATURE_RDSR2_0x15 includes FEATURE_WRSR_EXT2. */
+ if ((feature_bits & FEATURE_RDSR2_0x15) == FEATURE_RDSR2_0x15) {
+ read_cmd = 0x15;
+ break;
+ }
if (feature_bits & (FEATURE_WRSR_EXT2 | FEATURE_WRSR2)) {
read_cmd = JEDEC_RDSR2;
break;
@@ -226,13 +214,6 @@
}
msg_cerr("Cannot read SECURITY: unsupported by chip\n");
return 1;
- case CONFIG:
- if (feature_bits & FEATURE_CFGR) {
- read_cmd = JEDEC_RDCR;
- break;
- }
- msg_cerr("Cannot read CONFIG: unsupported by chip\n");
- return 1;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;
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