Anastasia Klimchuk submitted this change.

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Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved
it87spi.c: Allow passing programmer_cfg directly

Modify the type signature of the programmer entry-point
xxx_init() functions to allow for the consumption of the
programmer parameterisation string data.

Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
---
M include/programmer.h
M internal.c
M it87spi.c
3 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/include/programmer.h b/include/programmer.h
index 95e25ca..1372e2b 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -372,7 +372,7 @@
void enter_conf_mode_ite(uint16_t port);
void exit_conf_mode_ite(uint16_t port);
void probe_superio_ite(void);
-int init_superio_ite(void);
+int init_superio_ite(const struct programmer_cfg *cfg);

#if CONFIG_LINUX_MTD == 1
/* trivial wrapper to avoid cluttering internal_init() with #if */
diff --git a/internal.c b/internal.c
index 66eebdc..8b97f53 100644
--- a/internal.c
+++ b/internal.c
@@ -293,7 +293,7 @@
#if defined(__i386__) || defined(__x86_64__)
/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
- init_superio_ite();
+ init_superio_ite(cfg);

if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
msg_perr("Aborting to be safe.\n");
diff --git a/it87spi.c b/it87spi.c
index 568d714..bef60cb 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -321,7 +321,7 @@
.probe_opcode = default_spi_probe_opcode,
};

-static uint16_t it87spi_probe(uint16_t port)
+static uint16_t it87spi_probe(const struct programmer_cfg *cfg, uint16_t port)
{
uint8_t tmp = 0;
uint16_t flashport = 0;
@@ -440,7 +440,7 @@
return register_spi_master(&spi_master_it87xx, data);
}

-int init_superio_ite(void)
+int init_superio_ite(const struct programmer_cfg *cfg)
{
int i;
int ret = 0;
@@ -458,7 +458,7 @@
case 0x8718:
case 0x8720:
case 0x8728:
- ret |= it87spi_probe(superios[i].port);
+ ret |= it87spi_probe(cfg, superios[i].port);
break;
default:
msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",

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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab
Gerrit-Change-Number: 66662
Gerrit-PatchSet: 9
Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org>
Gerrit-Reviewer: Anastasia Klimchuk <aklm@chromium.org>
Gerrit-Reviewer: Felix Singer <felixsinger@posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged