Edward O'Callaghan has uploaded this change for review.

View Change

spi25_statusreg: implement w25q_write_status_register()

Change-Id: Idd9f818cb3464b3221330e7aa66f44b2b6d2adf7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M chipdrivers.h
M spi25_statusreg.c
2 files changed, 24 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/45749/1

diff --git a/chipdrivers.h b/chipdrivers.h
index 4e76588..c2764b9 100644
--- a/chipdrivers.h
+++ b/chipdrivers.h
@@ -65,6 +65,7 @@
 uint8_t spi_read_status_register(const struct flashctx *flash);
 uint8_t spi_read_status_register_2(const struct flashctx *flash);
 int spi_write_status_register(const struct flashctx *flash, int status);
+int w25q_write_status_register(const struct flashctx *flash, uint8_t s0, uint8_t s1);
 void spi_prettyprint_status_register_bit(uint8_t status, int bit);
 int spi_prettyprint_status_register_plain(struct flashctx *flash);
 int spi_prettyprint_status_register_default_welwip(struct flashctx *flash);
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index cad92e6..fb49c96 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -27,6 +27,15 @@
 	int result;
 	int i = 0;
 	/*
+	 * W25Q adds an optional byte to the standard WRSR opcode. If /CS is
+	 * de-asserted after the first byte, then it acts like a JEDEC-standard
+	 * WRSR command. if /CS is asserted, then the next data byte is written
+	 * into status register 2.
+	 */
+	uint8_t s0 = status & 0xff;
+	uint8_t s1 = (status >> 8) & 0xff;
+
+	/*
 	 * WRSR requires either EWSR or WREN depending on chip type.
 	 * The code below relies on the fact hat EWSR and WREN have the same
 	 * INSIZE and OUTSIZE.
@@ -38,8 +47,8 @@
 		.readcnt	= 0,
 		.readarr	= NULL,
 	}, {
-		.writecnt	= JEDEC_WRSR_OUTSIZE,
-		.writearr	= (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
+		.writecnt	= s1 > 0 ? (JEDEC_WRSR_OUTSIZE + 1) /* W25Q_WRSR_OUTSIZE */ : JEDEC_WREN_OUTSIZE,
+		.writearr	= (const unsigned char[]){ JEDEC_WRSR, s0, s1 },
 		.readcnt	= 0,
 		.readarr	= NULL,
 	}, {
@@ -90,6 +99,18 @@
 	return ret;
 }
 
+int w25q_write_status_register(const struct flashctx *flash, uint8_t s0, uint8_t s1)
+{
+	int feature_bits = flash->chip->feature_bits;
+	int ret = 1;
+
+	if (!(feature_bits & FEATURE_WRSR_WREN))
+		msg_cdbg("Missing status register write definition\n");
+	if (feature_bits & FEATURE_WRSR_WREN)
+		ret = spi_write_status_register_flag(flash, ((s1 << 8) | s0), JEDEC_WREN);
+	return ret;
+}
+
 static uint8_t spi_read_status_register_generic(const struct flashctx *flash, uint8_t opcode)
 {
 	const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { opcode };

To view, visit change 45749. To unsubscribe, or for help writing mail filters, visit settings.