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3 comments:
Commit Message:
File ichspi.c:
Patch Set #1, Line 1390: REGREAD32
> Isn't this register 16-bit? […]
Ack
Patch Set #1, Line 1392: } while ((hsfsts & HSFS_SCIP) == HSFS_SCIP);
This loop could potentially never exit.
It depends on HW operation and here is what EDS says, so, I believe we might not run into such issue. Also, *Software must only program the next command when this bit is 0.*
SPI Cycle In Progress (H_SCIP): Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register.
This bit remains set until the cycle completes on the SPI interface. Hardware
automatically sets and clears this bit so that software can determine when read data
is valid and/or when it is safe to begin programming the next command.
Software must only program the next command when this bit is 0.
This will ensure synchronisation in operations while using flashrom concurrently.
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