Nico Huber submitted this change.
ichspi: Replace default JEDEC_BE_D8 with JEDEC_SE
This aligns the upstream master branch with chromium's. On-the-fly
opcode reprogramming is supported by both branches so the default
opcode shouldn't matter.
Review URL: http://codereview.chromium.org/3239001
Change-Id: I379549e8fa966e75e3d8b7932700df62cf50df64
Signed-off-by: Mayur Panchal <panchalm@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
M ichspi.c
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ichspi.c b/ichspi.c
index 5a86c96..12ee126 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -324,7 +324,7 @@
{
{JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
{JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
- {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
+ {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
{JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
{JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
{JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
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