Edward O'Callaghan has uploaded this change for review.
intel: Add Alder Lake support [WIP]
Get this moving for Intel.
BUG=b:XXX
TEST=<none>
Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 30 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/62251/1
diff --git a/chipset_enable.c b/chipset_enable.c
index d9a1d3a..faa4ac2 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -607,6 +607,7 @@
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
reg_name = "BIOS_SPI_BC";
gcs = pci_read_long(dev, 0xdc);
@@ -712,6 +713,7 @@
boot_straps = boot_straps_pch500;
break;
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
boot_straps = boot_straps_apl;
@@ -742,6 +744,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
bbs = (gcs >> 6) & 0x1;
@@ -1008,6 +1011,10 @@
{
return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE);
}
+static int enable_flash_ald(struct pci_dev *const dev, const char *const name)
+{
+ return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_ALDER_LAKE);
+}
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
@@ -2111,6 +2118,7 @@
{0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
{0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
{0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
+ {0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake", enable_flash_adl},
{0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk},
{0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk},
{0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc},
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 0ce5720..6e64858 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -40,6 +40,7 @@
{
switch (cs) {
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
return 6;
case CHIPSET_C620_SERIES_LEWISBURG:
@@ -72,6 +73,7 @@
switch (cs) {
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
if (cont->NM <= MAX_NUM_MASTERS)
@@ -207,6 +209,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE: {
uint8_t size_enc;
@@ -297,6 +300,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
return freq_str[1][value];
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
return freq_str[2][value];
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -347,6 +351,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
has_flill1 = true;
@@ -528,7 +533,8 @@
desc->master.mstr[i].write & (1 << j) ? 'w' : ' ');
msg_pdbg2("\n");
}
- } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE || cs == CHIPSET_ELKHART_LAKE) {
+ } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_ALDER_LAKE
+ || cs == CHIPSET_GEMINI_LAKE || cs == CHIPSET_ELKHART_LAKE) {
const char *const master_names[] = { "BIOS", "TXE", };
if (nm > (ssize_t)ARRAY_SIZE(master_names)) {
msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM);
@@ -996,6 +1002,8 @@
if (content->FLMAP2 == 0) {
if (content->ISL == 19)
return CHIPSET_APOLLO_LAKE;
+ if (content->ISL == 19) // XXX ???
+ return CHIPSET_ALDER_LAKE;
if (content->ISL == 23)
return CHIPSET_GEMINI_LAKE;
warn_peculiar_desc("Gemini Lake");
@@ -1054,6 +1062,7 @@
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
/* `freq_read` was repurposed, so can't check on it any more. */
@@ -1211,6 +1220,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
if (idx == 0) {
@@ -1250,6 +1260,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
mmio_le_writel(control, spibar + PCH100_REG_FDOC);
diff --git a/ichspi.c b/ichspi.c
index 117ff8d..15ce568 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1782,6 +1782,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
*num_pr = 6; /* Includes GPR0 */
@@ -1818,6 +1819,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
*num_freg = 16;
@@ -1876,6 +1878,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
@@ -1953,6 +1956,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_BAYTRAIL:
case CHIPSET_ELKHART_LAKE:
@@ -1989,6 +1993,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_APOLLO_LAKE:
+ case CHIPSET_ALDER_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
break;
@@ -2029,6 +2034,7 @@
if (ich_spi_mode == ich_auto &&
(ich_gen == CHIPSET_APOLLO_LAKE ||
+ ich_gen == CHIPSET_ALDER_LAKE ||
ich_gen == CHIPSET_GEMINI_LAKE ||
ich_gen == CHIPSET_ELKHART_LAKE)) {
msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
diff --git a/programmer.h b/programmer.h
index 08e5e9c..376b819 100644
--- a/programmer.h
+++ b/programmer.h
@@ -351,6 +351,7 @@
CHIPSET_400_SERIES_COMET_POINT,
CHIPSET_500_SERIES_TIGER_POINT,
CHIPSET_APOLLO_LAKE,
+ CHIPSET_ALDER_LAKE,
CHIPSET_GEMINI_LAKE,
CHIPSET_ELKHART_LAKE,
};
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index f743510..6030a0b 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -127,6 +127,7 @@
"\t- \"ich10\",\n"
"\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n"
"\t- \"apollo\" for Intel's Apollo Lake SoC.\n"
+"\t- \"alder\" for Intel's Alder Lake SoC.\n"
"\t- \"gemini\" for Intel's Gemini Lake SoC.\n"
"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n"
"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n"
@@ -236,6 +237,8 @@
cs = CHIPSET_500_SERIES_TIGER_POINT;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
+ else if (strcmp(csn, "alder") == 0)
+ cs = CHIPSET_ALDER_LAKE;
else if (strcmp(csn, "gemini") == 0)
cs = CHIPSET_GEMINI_LAKE;
else if (strcmp(csn, "elkhart") == 0)
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