Anastasia Klimchuk submitted this change.
flashchips: Add chip models GD25LB256F/GD25LR256F
GD25LB256F: 1.8V 256Mbit
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-00978-GD25LB256F-Rev1.0.pdf
GD25LR256F: 1.8V 256Mbit with RPMC.
https://www.gigadevice.com/message-board?cid=39&id=3171&file_type=Datasheet&file_name=GD25LR256F
Tested Erase, write, read, and protection.
Change-Id: I0fbd270a57999d4131816c48470588bb7ec22d37
Signed-off-by: Victor <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
---
M flashchips.c
1 file changed, 57 insertions(+), 0 deletions(-)
diff --git a/flashchips.c b/flashchips.c
index 1a7954c..c34bafb 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6953,6 +6953,63 @@
},
{
+ .vendor = "GigaDevice",
+ .name = "GD25LB256F/GD25LR256F",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25LQ255E,
+ .total_size = 32768,
+ .page_size = 256,
+ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_5C,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {1650, 2000},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
+ .cmp = {STATUS2, 6, RW},
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
.vendor = "GigaDevice",
.name = "GD25LR512ME",
.bustype = BUS_SPI,
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