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1 comment:
Patchset:
Patch Set #2:
While you are flashing the SPI using flashrom on DUT at S0, there are cases when we are seeing some flashrom failure issue and debug data that we have so far is not very conclusive to say that CSE is doing anything wrong.
Was upstream flashrom used? Why do you assume that the CSE is involved?
I would expect the hardware to coordinate between the different masters. At least,
the SCIP bit can never be enough to synchronize masters. Even with the added
waiting loop, there is still much room for race conditions (e.g. second master
reading SCIP = 0 before the first posted its write to start a cycle).
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