Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen.
10 comments:
Patchset:
Thanks for the suggestions!
File doc/contrib_howtos/how_to_add_new_chip.rst:
Feature Bits
-------------
This can be on the same level as "Properties", especially because you have future plans to gradually […]
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The ``.feature_bits`` field in a chip definition encodes various features using a bitmask.
Here are some of the selected feature bits that need to be highlighted:
With this, we don't need an item in a list inside Properties. […]
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Write-Status-Register (WRSR) Handling
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This header also goes on level up, use `-`
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``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**.
I think this sentence is not needed. […]
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AFAIK it should be SPI only.
Move the "SPI only" hints into the next section instead.
Delete "This", start with "Indicates that"
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I noticed that it actually doesn't jump to a newline after EWSR, e.g.
```
FEATURE_WRSR_EWSR indicates that we need an Enable-Write-Status-Register
(EWSR) instruction which opens the status register for the immediately-followed
next WRSR instruction. Usually, the opcode is 0x50.
```
So I used the "indicates" with lowercase and remove the ":"
same
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Patch Set #1, Line 125: priort
typo, prior
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same
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Write-Status-Register (WRSR) Handling
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**.
The Write Status Register (WRSR) is used to configure various settings within the flash chip, including write protection and
other features. The way WRSR is accessed varies between SPI flash chips, leading to the need for these feature bits.
* ``FEATURE_WRSR_EWSR``:
This indicates that we need an **Enable-Write-Status-Register** (EWSR) instruction which opens the status register for the
immediately-followed next WRSR instruction. Usually, the opcode is **0x50**.
* ``FEATURE_WRSR_WREN``:
This indicates that we need an **Write-Enable** (WREN) instruction to set the Write Enable Latch (WEL) bit. The WEL bit
must be set priort to every WRSR command. Usually, the opcode is **0x06**.
* ``FEATURE_WRSR_EITHER``:
This indicates that either EWSR or WREN is supported in this chip.
Thank you for explaining! It's really good that I know your future plans. […]
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