Edward O'Callaghan has uploaded this change for review.
tree/: Remove internal_buses_support from global scope
Finally the buses_supported by the internal programmer
can be packed up into the board_cfg substructure and
out of the global symbol scope.
TEST=`$ sudo ./flashrom -p internal --flash-name`.
Change-Id: I987f2726acbf78e0294f8977f5a1734d2350405e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M board_enable.c
M chipset_enable.c
M ichspi.c
M include/programmer.h
M internal.c
M internal_par.c
M it87spi.c
7 files changed, 38 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/73464/1
diff --git a/board_enable.c b/board_enable.c
index 1ed1c5d..efb4131 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -606,7 +606,7 @@
uint8_t tmp;
int ret = 0;
- if (!(internal_buses_supported & BUS_PARALLEL))
+ if (!(bcfg->internal_buses_supported & BUS_PARALLEL))
return 1;
enter_conf_mode_ite(port);
@@ -614,7 +614,7 @@
/* Check if at least one flash segment is enabled. */
if (tmp & 0xf0) {
/* The IT8705F will respond to LPC cycles and translate them. */
- internal_buses_supported &= BUS_PARALLEL;
+ bcfg->internal_buses_supported &= BUS_PARALLEL;
/* Flash ROM I/F Writes Enable */
tmp |= 0x04;
msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
diff --git a/chipset_enable.c b/chipset_enable.c
index 0747d57..84206b2 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -72,13 +72,13 @@
tmp = pci_read_byte(dev, 0x40) & 0x3;
switch (tmp) {
case 3:
- internal_buses_supported &= BUS_FWH;
+ cfg->bcfg->internal_buses_supported &= BUS_FWH;
break;
case 2:
- internal_buses_supported &= BUS_LPC;
+ cfg->bcfg->internal_buses_supported &= BUS_LPC;
break;
default:
- internal_buses_supported &= BUS_PARALLEL;
+ cfg->bcfg->internal_buses_supported &= BUS_PARALLEL;
break;
}
@@ -228,7 +228,7 @@
uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
- internal_buses_supported &= BUS_PARALLEL;
+ cfg->bcfg->internal_buses_supported &= BUS_PARALLEL;
old = pci_read_word(dev, xbcs);
@@ -563,7 +563,7 @@
if ((err = enable_flash_ich_fwh_decode(cfg, dev, ich_generation)) != 0)
return err;
- internal_buses_supported &= BUS_FWH;
+ cfg->bcfg->internal_buses_supported &= BUS_FWH;
return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
}
@@ -1064,7 +1064,7 @@
if (ret_fwh == ERROR_FLASHROM_FATAL)
return ret_fwh;
- internal_buses_supported &= BUS_FWH;
+ cfg->bcfg->internal_buses_supported &= BUS_FWH;
/* Get physical address of SPI Base Address and map it */
uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
@@ -1218,7 +1218,7 @@
#define CS5530_ENABLE_SA2320 (1 << 2)
#define CS5530_ENABLE_SA20 (1 << 6)
- internal_buses_supported &= BUS_PARALLEL;
+ cfg->bcfg->internal_buses_supported &= BUS_PARALLEL;
/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
* FIXME: Should we really touch the low mapping below 1 MB? Flashrom
@@ -1406,7 +1406,7 @@
msg_pdbg("done.\n");
}
- internal_buses_supported &= BUS_LPC | BUS_FWH;
+ cfg->bcfg->internal_buses_supported &= BUS_LPC | BUS_FWH;
ret = sb600_probe_spi(cfg, dev);
@@ -1554,7 +1554,7 @@
{
uint8_t tmp;
- internal_buses_supported &= BUS_PARALLEL;
+ cfg->bcfg->internal_buses_supported &= BUS_PARALLEL;
tmp = INB(0xc06);
tmp |= 0x1;
@@ -1643,7 +1643,7 @@
switch ((val >> 5) & 0x3) {
case 0x0:
ret = enable_flash_mcp55(cfg, dev, name);
- internal_buses_supported &= BUS_LPC;
+ cfg->bcfg->internal_buses_supported &= BUS_LPC;
msg_pdbg("Flash bus type is LPC\n");
break;
case 0x2:
@@ -1651,12 +1651,12 @@
/* SPI is added in mcp6x_spi_init if it works.
* Do we really want to disable LPC in this case?
*/
- internal_buses_supported = BUS_NONE;
+ cfg->bcfg->internal_buses_supported = BUS_NONE;
msg_pdbg("Flash bus type is SPI\n");
break;
default:
/* Should not happen. */
- internal_buses_supported = BUS_NONE;
+ cfg->bcfg->internal_buses_supported = BUS_NONE;
msg_pwarn("Flash bus type is unknown (none)\n");
msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n"
"flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n"
@@ -2229,7 +2229,7 @@
"flashrom@flashrom.org including a verbose "
"(-V) log.\nThank you!\n");
}
- if (!(chipset_enables[i].buses & (internal_buses_supported | BUS_SPI))) {
+ if (!(chipset_enables[i].buses & (cfg->bcfg->internal_buses_supported | BUS_SPI))) {
msg_pdbg("Skipping chipset enable: No supported buses enabled.\n");
continue;
}
diff --git a/ichspi.c b/ichspi.c
index 0d3dd0e..d8f0196 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -2394,7 +2394,7 @@
/* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
/* Not sure if it speaks all these bus protocols. */
- internal_buses_supported &= BUS_LPC | BUS_FWH;
+ cfg->bcfg->internal_buses_supported &= BUS_LPC | BUS_FWH;
ich_generation = CHIPSET_ICH7;
register_spi_master(&spi_master_via, NULL);
diff --git a/include/programmer.h b/include/programmer.h
index 97c5e81..2477c80 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -167,6 +167,7 @@
struct board_cfg {
int is_laptop;
bool laptop_ok;
+ enum chipbustype internal_buses_supported;
};
struct board_match {
@@ -275,7 +276,6 @@
extern bool force_boardmismatch;
void probe_superio(void);
int register_superio(struct superio s);
-extern enum chipbustype internal_buses_supported;
#endif
/* bitbang_spi.c */
diff --git a/internal.c b/internal.c
index 071ea51..bba7043 100644
--- a/internal.c
+++ b/internal.c
@@ -29,8 +29,6 @@
bool force_boardmismatch = false;
-enum chipbustype internal_buses_supported = BUS_NONE;
-
static int get_params(const struct programmer_cfg *cfg,
bool *boardenable, bool *boardmismatch,
@@ -164,7 +162,7 @@
* is found, the host controller init routine sets the
* internal_buses_supported bitfield.
*/
- internal_buses_supported = BUS_NONSPI;
+ bcfg.internal_buses_supported = BUS_NONSPI;
if (try_mtd(cfg) == 0) {
ret = 0;
@@ -229,7 +227,7 @@
* non-legacy buses (SPI and opaque atm) are probed anyway.
*/
if (bcfg.is_laptop && !(bcfg.laptop_ok || force_laptop || (not_a_laptop && bcfg.is_laptop == 2)))
- internal_buses_supported = BUS_NONE;
+ bcfg.internal_buses_supported = BUS_NONE;
/* try to enable it. Failure IS an option, since not all motherboards
* really need this to be done, etc., etc.
@@ -257,7 +255,7 @@
}
#endif
- internal_par_init(internal_buses_supported);
+ internal_par_init(bcfg.internal_buses_supported);
/* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */
report_nonwl_laptop_detected(&bcfg);
diff --git a/internal_par.c b/internal_par.c
index e8e387c..031123e 100644
--- a/internal_par.c
+++ b/internal_par.c
@@ -75,5 +75,5 @@
void internal_par_init(enum chipbustype buses)
{
if (buses & BUS_NONSPI)
- register_par_master(&par_master_internal, internal_buses_supported, NULL);
+ register_par_master(&par_master_internal, buses, NULL);
}
diff --git a/it87spi.c b/it87spi.c
index dd9ab71..9e231f5 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -435,7 +435,7 @@
data->flashport = flashport;
data->fast_spi = true;
- if (internal_buses_supported & BUS_SPI)
+ if (cfg->bcfg->internal_buses_supported & BUS_SPI)
msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
/* FIXME: Add the SPI bus or replace the other buses with it? */
return register_spi_master(&spi_master_it87xx, data);
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