Attention is currently required from: Nico Huber, Paul Menzel.

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2 comments:

• File chipset_enable.c:

  • Patch Set #3, Line 659: { "eSPI", BUS_LPC | BUS_FWH } };

    I still wonder if eSPI is a bus for flashes at all? See […]

    https://downloadmirror.intel.com/27055/eng/329957-001_eSPI_Spec_Server_Addendum_Rev0_7.pdf
    Section 2 Slave Attached Flash Sharing

    So the eSPI bus may be used to access the SPI flash and according to section 2.3 there are flash erase and write ops as well. Although it does not use standard SPI protocol and truly `there is nothing to be done for eSPI atm`. It depends on what we want to have there (reserved or eSPI) to be displayed.

• File chipset_enable.c:

  • Patch Set #10, Line 657: _lp

    The `lp` suffix was previously used when there was a low-power version […]

    I think they will have the same buses for flash either way.

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