Attention is currently required from: Xiang W, Edward O'Callaghan, Angel Pons.
2 comments:
Commit Message:
Patch Set #26, Line 11: may not be
This "may not be" is rather vague. […]
I will not comment further on this review until this is answered.
File bitbang_spi.c:
programmer_delay(master->half_period);
bitbang_spi_set_sck_set_mosi(master, !cpol, (val >> i) & 1);
programmer_delay(master->half_period);
bitbang_spi_set_sck(master, cpol);
The hardware logic only requires that the data state is stable after the clock changes. […]
Hmm, what can I say more? Please have a careful look at the diagrams
in the Wikipedia article you linked and the datasheet of the chip you
used for testing.
Long story short, your (later corrected) order of signal changes is
eventually correct. But your delays are 100% off. You also have to
account for programmer drivers that change MOSI and CLK at once in
bitbang_spi_set_sck_set_mosi().
If you continue trying to correct your code, please also include
logic-analyzer traces before/after the patch and test programming
speed as well, so no prior, precious optimizations to this code
are lost.
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