Sergii Dmytruk has uploaded this change for review.
[RFC] dummyflasher: support emulation of SR2
This is needed for accessing second SRP bit which is involved in write
protection.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
M dummyflasher.c
1 file changed, 54 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/59072/1
diff --git a/dummyflasher.c b/dummyflasher.c
index 2311576..7ef4a25 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -43,6 +43,8 @@
int erase_to_zero;
int emu_modified; /* is the image modified since reading it? */
uint8_t emu_status;
+ uint8_t emu_status2;
+ uint8_t emu_status_len; /* number of emulated status bytes */
/* If "freq" parameter is passed in from command line, commands will delay
* for this period before returning. */
unsigned long int delay_us;
@@ -158,6 +160,12 @@
return;
}
+/* Status registers are base 1. */
+static uint8_t get_status_ro_bits(int status_reg)
+{
+ return (status_reg == 1 ? SPI_SR_WEL | SPI_SR_WIP : 0);
+}
+
static int emulate_spi_chip_response(unsigned int writecnt,
unsigned int readcnt,
const unsigned char *writearr,
@@ -165,6 +173,7 @@
struct emu_data *data)
{
unsigned int offs, i, toread;
+ uint8_t ro_bits;
static int unsigned aai_offs;
const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44};
const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a};
@@ -306,6 +315,10 @@
case JEDEC_RDSR:
memset(readarr, data->emu_status, readcnt);
break;
+ case JEDEC_RDSR2:
+ if (data->emu_status_len >= 2)
+ memset(readarr, data->emu_status2, readcnt);
+ break;
/* FIXME: this should be chip-specific. */
case JEDEC_EWSR:
case JEDEC_WREN:
@@ -316,9 +329,33 @@
msg_perr("WRSR attempted, but WEL is 0!\n");
break;
}
+
/* FIXME: add some reasonable simulation of the busy flag */
- data->emu_status = writearr[1] & ~SPI_SR_WIP;
- msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status);
+ ro_bits = get_status_ro_bits(1);
+ data->emu_status &= ro_bits;
+ data->emu_status |= (writearr[1] & ~ro_bits);
+ if (writecnt == 3) {
+ ro_bits = get_status_ro_bits(2);
+ data->emu_status2 &= ro_bits;
+ data->emu_status2 |= (writearr[2] & ~ro_bits);
+ }
+
+ if (writecnt == 3)
+ msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status2, data->emu_status);
+ else
+ msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status);
+ break;
+ case JEDEC_WRSR2:
+ if (data->emu_status_len < 2)
+ break;
+ if (!(data->emu_status & SPI_SR_WEL)) {
+ msg_perr("WRSR2 attempted, but WEL is 0!\n");
+ break;
+ }
+
+ ro_bits = get_status_ro_bits(2);
+ data->emu_status2 &= ro_bits;
+ data->emu_status2 |= (writearr[1] & ~ro_bits);
break;
case JEDEC_READ:
offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
@@ -811,6 +848,7 @@
data->emu_chip_size = 128 * 1024;
data->emu_max_byteprogram_size = 128;
data->emu_max_aai_size = 0;
+ data->emu_status_len = 1;
data->emu_jedec_se_size = 0;
data->emu_jedec_be_52_size = 0;
data->emu_jedec_be_d8_size = 32 * 1024;
@@ -824,6 +862,7 @@
data->emu_chip_size = 512 * 1024;
data->emu_max_byteprogram_size = 1;
data->emu_max_aai_size = 0;
+ data->emu_status_len = 1;
data->emu_jedec_se_size = 4 * 1024;
data->emu_jedec_be_52_size = 32 * 1024;
data->emu_jedec_be_d8_size = 0;
@@ -837,6 +876,7 @@
data->emu_chip_size = 4 * 1024 * 1024;
data->emu_max_byteprogram_size = 1;
data->emu_max_aai_size = 2;
+ data->emu_status_len = 1;
data->emu_jedec_se_size = 4 * 1024;
data->emu_jedec_be_52_size = 32 * 1024;
data->emu_jedec_be_d8_size = 64 * 1024;
@@ -850,6 +890,7 @@
data->emu_chip_size = 8 * 1024 * 1024;
data->emu_max_byteprogram_size = 256;
data->emu_max_aai_size = 0;
+ data->emu_status_len = 1;
data->emu_jedec_se_size = 4 * 1024;
data->emu_jedec_be_52_size = 32 * 1024;
data->emu_jedec_be_d8_size = 64 * 1024;
@@ -863,6 +904,7 @@
data->emu_chip_size = 16 * 1024 * 1024;
data->emu_max_byteprogram_size = 256;
data->emu_max_aai_size = 0;
+ data->emu_status_len = 1;
data->emu_jedec_se_size = 4 * 1024;
data->emu_jedec_be_52_size = 32 * 1024;
data->emu_jedec_be_d8_size = 64 * 1024;
@@ -927,8 +969,16 @@
return 1;
}
free(status);
- msg_pdbg("Initial status register is set to 0x%02x.\n",
- data->emu_status);
+
+ if (data->emu_status_len == 2) {
+ msg_pdbg("Initial status registers:\n"
+ "\tSR1 is set to 0x%02x\n"
+ "\tSR2 is set to 0x%02x\n",
+ data->emu_status, data->emu_status2);
+ } else {
+ msg_pdbg("Initial status register is set to 0x%02x.\n",
+ data->emu_status);
+ }
}
data->flashchip_contents = malloc(data->emu_chip_size);
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