Attention is currently required from: Bora Guvendik, Anil Kumar K, Nico Huber, Paul Menzel, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk.

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2 comments:

• Patchset:

  • Patch Set #7:

    +1, I remember some previous discussion now about some changes being needed to properly support these chipsets. I've removed my CR vote

• File chipset_enable.c:

  • Patch Set #7, Line 2018:

    {0x8086, 0xa224, B_FS,   OK,  "Intel", "Lewisburg",			enable_flash_pch100},
    	{0x8086, 0x9da4, B_FS,   OK,  "Intel", "Cannonlake",			enable_flash_pch100},
    	{0x8086, 0x34a4, B_FS,   OK,  "Intel", "Icelake",			enable_flash_pch100},
    	{0x8086, 0x4da4, B_FS,   OK,  "Intel", "Jasperlake",			enable_flash_pch100},
    	{0x8086, 0xa0a4, B_FS,   OK,  "Intel", "Tigerlake",			enable_flash_pch100},
    	{0x8086, 0x7aa4, B_FS,   OK,  "Intel", "Alderlake-S",			enable_flash_pch100},
    	{0x8086, 0x51a4, B_FS,   OK,  "Intel", "Alderlake-P / M",	        enable_flash_pch100},
    

    flashrom uses LPC/eSPI PCI IDs instead of SPI PCI IDs. […]

    +1, I remember seeing some discussion of the SPI device visibility issues now. I've removed my CR vote since we should use the LPC IDs.

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