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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 9:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/b837a580_44b983d1
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
: into below error:
:
: Erasing and writing flash chip... Timeout error between offset
: 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
: Uh oh. Erase/write failed. Checking if anything has changed.
> What I'm still missing is how it relates to the change.
isn't the observation and solution part being added in the commit msg is ample for you to understand how this changes are relevant in terms of perform sync the operation coming from different agents without having a file lock mechanism in place?
> AIUI, it's
> only the background story what led to its finding, and doesn't say
> anything about the change.
>
> I think it's generally ok to add such information (even though I
> don't see any value). But it must be clear how it relates to the
> change. Confusing information can be harmful, especially in commit
> messages that can't be changed later on.
https://review.coreboot.org/c/flashrom/+/61854/comment/51d97639_71895236
PS7, Line 24: BUG=b:215255210
> I don't see any answer. Please never again mark my comments as resolved.
>
> Please make sure all information on that issue tracker is sane, doesn't
> lead to further wrong assumptions about this change and can't be changed
> anymore, e.g. close the ticket. Or, just don't reference it.
Do you want me to update every post from bug b/215255210 to here? I have marked this comment resolved because I have updated the problem, observation and solution all together in this commit msg. Please be specific what you want to know from that bug.
https://review.coreboot.org/c/flashrom/+/61854/comment/88cad64c_e101b92b
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> Please also test older platforms, not just the newest (also, platforms
> that are not supported yet don't matter). If you need help with testing
> you can always ask on the mailing list and IRC.
Sorry, I don't have those older platform POC information. I will try to set a context with those owners informally. Looking at older platform EDS specification, I don't expect anything would behave differently there as this is same HW seq on Intel platform started with SKL. (you can always ask question about how since then so many years AU worked without this bit being implement on older platform, I don't have that answer either with me)
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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 29:
(1 comment)
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/ea655b2d_8a0c9373
PS29, Line 495: (uint8_t *)
Ah, I was too tired yesterday when I read this and didn't
see the cast. I guess this is what makes the verification
work by chance?
Such a cast is a no-go.
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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 29:
(2 comments)
Patchset:
PS29:
Not sure if it was mentioned before: Generally smaller patches
are preferred. Review doesn't scale well with the amount of lines
and commit messages tend to be far too thin. With 10 10-times
smaller patches, I generally expect 10-times faster review
compared to everything at once. This one would be hard to split
that much, but there are still ~4 independent topics here:
board checking, flashing, content compatibilty checking (does it
belong in flashrom?), the autoload option (does it belong in
flashrom?).
Don't know if it's too late to split.
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/93e4c8dd_2d3fa31d
PS29, Line 411: }
Doesn't this mean we always have to flash the whole chip? and all blocks in
order? Should we set the write granularity to the flash size in this case?
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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 29:
(1 comment)
Patchset:
PS29:
I'm not sure if I understand the `autoload` option correctly. Is it
altering the data to be flashed? If so, how does it work with veri-
fication?
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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 29:
(1 comment)
Patchset:
PS29:
> Now I probe only for ITE Super I/Os. Just added more model IDs in the switch to catch the supported chips. Redesigning Super I/O code needs more thought and I won't pursue it right now. DMI checks have been replaced with PCI ID and SSID checks to not depend on any dmidecoder (which may fail depending on UEFI vs legacy).
Generally, I'd prefer to simply hook this driver up in the
internal programmer. Then it would be easiest to use the
board_enable infrastructure and we wouldn't have to re-
invent it.
Alternatively, if you agree that the interface will change
significantly in the future, we can also keep the local
checks and add a FIXME comment that it actually belongs
into the internal programmer. Most of the programmer
drivers added lately do things wrong and I fear if we add
more bad examples these issues will become worse.
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 9:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/5e6a2858_62b327e0
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
: into below error:
:
: Erasing and writing flash chip... Timeout error between offset
: 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
: Uh oh. Erase/write failed. Checking if anything has changed.
> Ack
What I'm still missing is how it relates to the change. AIUI, it's
only the background story what led to its finding, and doesn't say
anything about the change.
I think it's generally ok to add such information (even though I
don't see any value). But it must be clear how it relates to the
change. Confusing information can be harmful, especially in commit
messages that can't be changed later on.
https://review.coreboot.org/c/flashrom/+/61854/comment/1456ac09_f7c86664
PS7, Line 24: BUG=b:215255210
> Ack
I don't see any answer. Please never again mark my comments as resolved.
Please make sure all information on that issue tracker is sane, doesn't
lead to further wrong assumptions about this change and can't be changed
anymore, e.g. close the ticket. Or, just don't reference it.
https://review.coreboot.org/c/flashrom/+/61854/comment/250702bc_21c0b6a6
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> Ack
Please also test older platforms, not just the newest (also, platforms
that are not supported yet don't matter). If you need help with testing
you can always ask on the mailing list and IRC.
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Hello build bot (Jenkins), Patrick Georgi, Stefan Reinauer, Rizwan Qureshi, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Caveh Jalali, Tim Wawrzynczak, Edward O'Callaghan, Nick Vaccaro, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#9).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit. Software must initiate
the next SPI transaction when this bit is 0.
Problem Statement:
Evidencing AU failure while performing firmware update on the Alder Lake
based ChromeOS devices.
Observation:
Based on the initial understanding from the failure log/pattern, it
seems like the platform is evidencing multiple `flashrom` access from
different source, for example: `futility` accesses flashrom for erase,
write and read operation, `crossystem` uses flashrom for updating VBNV,
additionally, `set_fw_good` script also uses `crossystem` to update the
fw status.
Solution:
Without this synchronisation being implemented in flashrom, there is no
way to ensure multiple instances of flashrom performing different SPI
operations are not cancelling each other and running into below error:
Erasing and writing flash chip... Timeout error between offset
0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
Uh oh. Erase/write failed. Checking if anything has changed.
BUG=b:215255210
TEST=Able to flash coreboot image on Alder Lake Brya variants, Tiger
Lake Volteer variants and Comet Lake Hatch variants without any failure.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/9
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 7:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/c25e76b4_51fd5a78
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
: into below error:
:
: Erasing and writing flash chip... Timeout error between offset
: 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
: Uh oh. Erase/write failed. Checking if anything has changed.
> If you want to mention this, please also describe the full setup, […]
Ack
https://review.coreboot.org/c/flashrom/+/61854/comment/45a29380_8e0b77b6
PS7, Line 24: BUG=b:215255210
> What's said in this issue and what's its status?
Ack
https://review.coreboot.org/c/flashrom/+/61854/comment/abe13130_17c167bb
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> Please also test that things still work on as many platforms as […]
Ack
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/61854/comment/0d273097_b35efddd
PS7, Line 1410: Error: SCIP never cleared!
> Maybe this would fit better:
>
> Error: SCIP bit is unexpectedly set.
ACK
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Hello build bot (Jenkins), Patrick Georgi, Stefan Reinauer, Rizwan Qureshi, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Caveh Jalali, Tim Wawrzynczak, Edward O'Callaghan, Nick Vaccaro, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#8).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit. Software must initiate
the next SPI transaction when this bit is 0.
Problem Statement:
Evidencing AU failure while performing firmware update on the Alder Lake
based ChromeOS devices.
Observation:
Based on the initial understanding from the failure log/pattern, it seems
like the platform is evidencing multiple `flashrom` access from different
source, for example: `futility` accesses flashrom for erase, write and read
operation, `crossystem` uses flashrom for updating VBNV, additionally,
`set_fw_good` script also uses `crossystem` to update the fw status.
Solution:
Without this synchronisation being implemented in flashrom, there is no way
to ensure multiple instances of flashrom performing different SPI operations
are not cancelling each other and running into below error:
Erasing and writing flash chip... Timeout error between offset
0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
Uh oh. Erase/write failed. Checking if anything has changed.
BUG=b:215255210
TEST=Able to flash coreboot image on Alder Lake Brya varients, Tiger Lake
Volteer varients and Comet Lake Hatch varients without any failure.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/8
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