July 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: lspcon_i2c_spi.c: Add debug message that shows the active block.
by Shiyu Sun (Code Review) Aug. 4, 2020

Aug. 4, 2020

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41779 ) Change subject: lspcon_i2c_spi.c: Add debug message that shows the active block. ...................................................................... lspcon_i2c_spi.c: Add debug message that shows the active block. This is all for debug propose to verify A/B update work as expected. BUG=b:148746232 BRANCH=none TEST=flashrom -p lspcon_i2c_spi:bus=7 --flash-size -V verified the related message appears. Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: I1b3022542f98f114097c6f39254ef4c2cf188c90 --- M lspcon_i2c_spi.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/41779/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..e5e5dc9 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -27,6 +27,7 @@ #define REGISTER_ADDRESS (0x94 >> 1) #define PAGE_ADDRESS (0x9e >> 1) +#define ACTIVE_BLOCK_ADDRESS (0x9a >> 1) #define PAGE_SIZE 256 #define MAX_SPI_WAIT_RETRIES 1000 @@ -472,6 +473,27 @@ return ret; } +static void lspcon_i2c_spi_boot_block_info(int fd) +{ + uint8_t block_id = 0; + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, 0xbc, 0xc0); + ret |= lspcon_i2c_spi_write_register(fd, 0xbc, 0x40); + ret |= lspcon_i2c_spi_write_register(fd, 0x8e, 0x00); + ret |= lspcon_i2c_spi_write_register(fd, 0x8f, 0x00); + struct timespec wait_10ms = { 0, (unsigned)1e7 }; + nanosleep(&wait_10ms, NULL); + + uint8_t command[] = { 0x0e }; + ret |= lspcon_i2c_spi_write_data(fd, ACTIVE_BLOCK_ADDRESS, command, 1); + ret |= lspcon_i2c_spi_read_data(fd, ACTIVE_BLOCK_ADDRESS, &block_id, 1); + if (ret) { + msg_pdbg("Failed to get LSPCON boot block information.\n"); + } else { + msg_pdbg("LSPCON is booting from block #%d.\n", block_id); + } +} + int lspcon_i2c_spi_init(void) { int lspcon_i2c_spi_bus = get_bus(); @@ -489,6 +511,9 @@ return ret; } + /* Show current activate block information for debug propose. */ + lspcon_i2c_spi_boot_block_info(fd); + struct lspcon_i2c_spi_data *data = calloc(1, sizeof(struct lspcon_i2c_spi_data)); if (!data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); -- To view, visit https://review.coreboot.org/c/flashrom/+/41779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1b3022542f98f114097c6f39254ef4c2cf188c90 Gerrit-Change-Number: 41779 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

5 8

Change in flashrom[master]: git-hooks: Add check-style for pre-commit hook
by David Hendricks (Code Review) Aug. 4, 2020

Aug. 4, 2020

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43602 ) Change subject: git-hooks: Add check-style for pre-commit hook ...................................................................... git-hooks: Add check-style for pre-commit hook This imports check-style and some related lint tools from coreboot for the pre-commit hook: - Add check-style rule to Makefile - Replace the current pre-commit hook with the one from coreboot, omitting lint-stable for the time being. - Import checkpatch.pl, along with certain dependencies (spelling.txt and const_structs.checkpatch) and .checkpatch.conf. - Add .clang-format from CB:38673. Change-Id: Ieb77aa1aa2911e081c69c93929a2f1c4430cd2b9 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- A .checkpatch.conf A .clang-format M Makefile M util/git-hooks/pre-commit A util/lint/check-style A util/lint/checkpatch.pl A util/lint/const_structs.checkpatch A util/lint/lint-007-checkpatch A util/lint/spelling.txt 9 files changed, 16,655 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/43602/1 -- To view, visit https://review.coreboot.org/c/flashrom/+/43602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieb77aa1aa2911e081c69c93929a2f1c4430cd2b9 Gerrit-Change-Number: 43602 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in flashrom[master]: meson: Do not compile with -DSTANDALONE
by Richard Hughes (Code Review) Aug. 4, 2020

Aug. 4, 2020

Richard Hughes has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42230 ) Change subject: meson: Do not compile with -DSTANDALONE ...................................................................... meson: Do not compile with -DSTANDALONE This enables the -o option which is used to collect logs for debugging. Change-Id: If6c12c682ba72cd519e30f1f8c96552322ff75e3 Signed-off-by: Richard Hughes <richard(a)hughsie.com> --- M meson.build 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/42230/1 diff --git a/meson.build b/meson.build index 5d8e630..4b00339 100644 --- a/meson.build +++ b/meson.build @@ -415,7 +415,6 @@ ], c_args : [ cargs, - '-DSTANDALONE', '-DCONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INVALID', '-DCONFIG_DEFAULT_PROGRAMMER_ARGS=""', ], -- To view, visit https://review.coreboot.org/c/flashrom/+/42230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If6c12c682ba72cd519e30f1f8c96552322ff75e3 Gerrit-Change-Number: 42230 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Hughes <richard(a)hughsie.com> Gerrit-MessageType: newchange

3 5

Change in flashrom[master]: ft2232_spi.c: align with Chrome OS flashrom
by Nikolai Artemiev (Code Review) Aug. 4, 2020

Aug. 4, 2020

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42796 ) Change subject: ft2232_spi.c: align with Chrome OS flashrom ...................................................................... ft2232_spi.c: align with Chrome OS flashrom Brings over various changes: - Limit servo channel selection to valid range - Use DIS_DIV_5 constant - Update some comments - Wrap long lines Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: I24c20e9b5d7e661d0180699bbd0d1447f6bf816f --- M ft2232_spi.c 1 file changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/42796/1 diff --git a/ft2232_spi.c b/ft2232_spi.c index 87e6057..083e58f 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -110,7 +110,8 @@ { int i; for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + if ((devs_ft2232spi[i].device_id == ft2232_type) + && (devs_ft2232spi[i].vendor_id == ft2232_vid)) return devs_ft2232spi[i].device_name; } return "unknown device"; @@ -120,7 +121,8 @@ { int i; for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + if ((devs_ft2232spi[i].device_id == ft2232_type) + && (devs_ft2232spi[i].vendor_id == ft2232_vid)) return devs_ft2232spi[i].vendor_name; } return "unknown vendor"; @@ -132,7 +134,8 @@ int r; r = ftdi_write_data(ftdic, (unsigned char *) buf, size); if (r < 0) { - msg_perr("ftdi_write_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); + msg_perr("ftdi_write_data: %d, %s\n", r, + ftdi_get_error_string(ftdic)); return 1; } return 0; @@ -146,7 +149,8 @@ while (size > 0) { r = ftdi_read_data(ftdic, (unsigned char *) buf, size); if (r < 0) { - msg_perr("ftdi_read_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); + msg_perr("ftdi_read_data: %d, %s\n", r, + ftdi_get_error_string(ftdic)); return 1; } buf += r; @@ -183,8 +187,8 @@ enum ftdi_interface ft2232_interface = INTERFACE_A; /* * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, - * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 - * prescaler on the former to run on the same speed. + * but the non-H chips can only run at 12 MHz. We disable the divide-by-5 + * prescaler on 'H' chips so they run at 60MHz. */ uint8_t clock_5x = 1; /* In addition to the prescaler mentioned above there is also another @@ -193,7 +197,8 @@ * div = (1 + x) * 2 <-> x = div / 2 - 1 * Hence the expressible divisors are all even numbers between 2 and * 2^17 (=131072) resulting in SCK frequencies of 6 MHz down to about - * 92 Hz for 12 MHz inputs. + * 92 Hz for 12 MHz inputs and 30 MHz down to about 458 Hz for 60 MHz + * inputs. */ uint32_t divisor = DEFAULT_DIVISOR; int f; @@ -268,14 +273,17 @@ } else if (!strcasecmp(arg, "google-servo")) { ft2232_vid = GOOGLE_VID; ft2232_type = GOOGLE_SERVO_PID; + channel_count = 2; } else if (!strcasecmp(arg, "google-servo-v2")) { ft2232_vid = GOOGLE_VID; ft2232_type = GOOGLE_SERVO_V2_PID1; + channel_count = 2; /* Default divisor is too fast, and chip ID fails */ divisor = 6; } else if (!strcasecmp(arg, "google-servo-v2-legacy")) { ft2232_vid = GOOGLE_VID; ft2232_type = GOOGLE_SERVO_V2_PID0; + channel_count = 2; } else if (!strcasecmp(arg, "flyswatter")) { ft2232_type = FTDI_FT2232H_PID; channel_count = 2; @@ -381,7 +389,8 @@ free(arg); if (f < 0 && f != -5) { - msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); + msg_perr("Unable to open FTDI device: %d (%s)\n", f, + ftdi_get_error_string(ftdic)); return -4; } @@ -408,7 +417,7 @@ if (clock_5x) { msg_pdbg("Disable divide-by-5 front stage\n"); - buf[0] = 0x8a; /* Disable divide-by-5. DIS_DIV_5 in newer libftdi */ + buf[0] = DIS_DIV_5; if (send_buf(ftdic, buf, 1)) { ret = -5; goto ftdi_err; @@ -453,7 +462,8 @@ ftdi_err: if ((f = ftdi_usb_close(ftdic)) < 0) { - msg_perr("Unable to close FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); + msg_perr("Unable to close FTDI device: %d (%s)\n", f, + ftdi_get_error_string(ftdic)); } return ret; } -- To view, visit https://review.coreboot.org/c/flashrom/+/42796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I24c20e9b5d7e661d0180699bbd0d1447f6bf816f Gerrit-Change-Number: 42796 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [stlinkv3_spi]Added missing line ends, and added a note about the fir...
by Miklós Márton (Code Review) Aug. 4, 2020

Aug. 4, 2020

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43900 ) Change subject: [stlinkv3_spi]Added missing line ends, and added a note about the first version of the updater which contains the necessary V3 bridge feature. ...................................................................... [stlinkv3_spi]Added missing line ends, and added a note about the first version of the updater which contains the necessary V3 bridge feature. Change-Id: Ib45efa37b192489bdfe26f1f0fd1d81035a08c70 Signed-off-by: Miklós Márton <martonmiklosqdev(a)gmail.com> --- M stlinkv3_spi.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/00/43900/1 diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index ae865be..c75f7db 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -253,21 +253,22 @@ enum fw_version_check_result fw_check_result; if (stlinkv3_check_version(&fw_check_result)) { - msg_perr("Failed to query FW version"); + msg_perr("Failed to query FW version\n"); return -1; } if (fw_check_result != FW_VERSION_OK) { msg_pinfo("Your STLink V3 has too old version of the bridge interface\n" - "Please update the firmware with the STSW-LINK007 which can be downloaded from here:\n" - "https://www.st.com/en/development-tools/stsw-link007.html"); + "Please update the firmware with version 2.33.25 or newer of the STSW-LINK007\n" + "which can be downloaded from here:\n" + "https://www.st.com/en/development-tools/stsw-link007.html\n"); return -1; } if (stlinkv3_spi_calc_prescaler(reqested_freq_in_kHz, &prescaler, &SCK_freq_in_kHz)) { - msg_perr("Failed to calculate SPI clock prescaler"); + msg_perr("Failed to calculate SPI clock prescaler\n"); return -1; } msg_pinfo("SCK frequency set to %d kHz\n", SCK_freq_in_kHz); -- To view, visit https://review.coreboot.org/c/flashrom/+/43900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib45efa37b192489bdfe26f1f0fd1d81035a08c70 Gerrit-Change-Number: 43900 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Simon Buhrow (Code Review) July 27, 2020

July 27, 2020

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 14: Just a try to show what effect the change has: To do one PageProgram the Flash needs the following cmds/information (PROG=PageProgramCmd): Flash-Cmds: JEDEC_WREN + PROG + ADDR + DATA As flashrom communicates with the FTDI, there are additional FTDI-cmds necessary, of course. This gives the following calls: ft2232_spi_send_command(XX, XX, ['JEDEC_WREN'], XX) before: -> send_buf(XX, [FTDI-CMD + 'JEDEC_WREN' + FTDI-CMD], 10) now: -> save i and buf as they are static, no further function call; buf = [FTDI-CMD + 'JEDEC_WREN' + FTDI-CMD] ft2232_spi_send_command(XX, XX, ['PROG', 'ADDR', 'DATA'], XX) before: -> send_buf(XX, [FTDI-CMD + 'PROG' + 'ADDR' + 'DATA' + FTDI-CMD], 270) now: -> send_buf(XX, [FTDI-CMD + 'JEDEC_WREN' + FTDI-CMD + FTDI-CMD + 'PROG' + 'ADDR' + 'DATA' + FTDI-CMD], 280) => saves one send_buf/ftdi_write_data call every page-program or erase action. -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 14 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 27 Jul 2020 14:16:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: ich_descriptors.h: Upstream PCH100+ region comment
by Edward O'Callaghan (Code Review) July 26, 2020

July 26, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43896 ) Change subject: ich_descriptors.h: Upstream PCH100+ region comment ...................................................................... ich_descriptors.h: Upstream PCH100+ region comment Useful information we should extract out of the chromium fork of flashrom and ingest into upstream. Change-Id: I246c56aa86bb44f27c5934ab5883f555a8307784 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ich_descriptors.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/43896/1 diff --git a/ich_descriptors.h b/ich_descriptors.h index c6bf5d8..98535e1 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -234,6 +234,14 @@ :3; }; /* From Skylake on */ + /* + * Flash Descriptor Master Access settings for PCH100+ + * + * [31:20] Master Region Write Access (regions 11:0) + * [19:8] Master Region Read Access (regions 11:0) + * [7:4] Extended Region Write Access (regions 15:12) + * [3:0] Extended Region Read access (regions 15:12) + */ struct { uint32_t ext_read :4, ext_write :4, -- To view, visit https://review.coreboot.org/c/flashrom/+/43896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I246c56aa86bb44f27c5934ab5883f555a8307784 Gerrit-Change-Number: 43896 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Take chromiums flash desc sec override msg
by Edward O'Callaghan (Code Review) July 26, 2020

July 26, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43895 ) Change subject: ichspi.c: Take chromiums flash desc sec override msg ...................................................................... ichspi.c: Take chromiums flash desc sec override msg Line wrapped and a little more descriptive. Change-Id: I1043bed042f5507788ed2b417bd44d0fe3dc0aa6 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/43895/1 diff --git a/ichspi.c b/ichspi.c index 1cc1cd7..d9f13ef 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1849,9 +1849,11 @@ if (tmp2 & HSFS_FDV) desc_valid = 1; if (!(tmp2 & HSFS_FDOPSS) && desc_valid) - msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" - "the Master Section of the flash descriptor are NOT in effect. Please note\n" - "that Protected Range (PR) restrictions still apply.\n"); + msg_pinfo("The Flash Descriptor Security Override " + "Strap-Pin is set. Restrictions implied\n" + "by the FRAP and FREG registers are NOT in " + "effect. Please note that Protected\n" + "Range (PR) restrictions still apply.\n"); ich_init_opcodes(ich_gen); if (desc_valid) { -- To view, visit https://review.coreboot.org/c/flashrom/+/43895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1043bed042f5507788ed2b417bd44d0fe3dc0aa6 Gerrit-Change-Number: 43895 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Consolidate ich_spi_mode select into a switch stmt
by Edward O'Callaghan (Code Review) July 26, 2020

July 26, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43894 ) Change subject: ichspi.c: Consolidate ich_spi_mode select into a switch stmt ...................................................................... ichspi.c: Consolidate ich_spi_mode select into a switch stmt Change-Id: I35535c3dac9fa796d204d60e5fc72a7d5f85d706 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/43894/1 diff --git a/ichspi.c b/ichspi.c index 4dbe69a..1cc1cd7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2002,16 +2002,18 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && - (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { - msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); - ich_spi_mode = ich_hwseq; - } - - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { - msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); - ich_spi_mode = ich_hwseq; + if (ich_spi_mode == ich_auto) { + switch (ich_gen) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_APOLLO_LAKE: + msg_pdbg("Enabling hardware sequencing by default " + "for 100+ series PCH.\n"); + ich_spi_mode = ich_hwseq; + break; + default: + break; + } } if (ich_spi_mode == ich_hwseq) { -- To view, visit https://review.coreboot.org/c/flashrom/+/43894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I35535c3dac9fa796d204d60e5fc72a7d5f85d706 Gerrit-Change-Number: 43894 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: Add support for Winbond W25X05CL
by Miklós Márton (Code Review) July 26, 2020

July 26, 2020

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43573 ) Change subject: Add support for Winbond W25X05CL ...................................................................... Add support for Winbond W25X05CL This commit adds support for the Winbond W25X05CL SPI flash chip. The Winbond W25X05CL is a 512K-BIT SPI flash chip with 4KB sectors. I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL flash chip using a test clip. Reading, erasing, and writing all function as expected. Datasheet: http://www.winbond.com/resource-files/w25x05cl_f%2004252017.pdf Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc Signed-off-by: Jacob Appelbaum <jacob(a)appelbaum.net> --- M flashchips.c M flashchips.h 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/43573/1 diff --git a/flashchips.c b/flashchips.c index 48405fe..3d8042d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -17329,6 +17329,38 @@ { .vendor = "Winbond", + .name = "W25X05", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25X05, + .total_size = 64, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2300, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25X10", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index c58595d..f6e2588 100644 --- a/flashchips.h +++ b/flashchips.h @@ -917,6 +917,7 @@ #define WINBOND_NEX_W25P80 0x2014 #define WINBOND_NEX_W25P16 0x2015 #define WINBOND_NEX_W25P32 0x2016 +#define WINBOND_NEX_W25X05 0x3010 /* W25X05CL */ #define WINBOND_NEX_W25X10 0x3011 #define WINBOND_NEX_W25X20 0x3012 #define WINBOND_NEX_W25X40 0x3013 -- To view, visit https://review.coreboot.org/c/flashrom/+/43573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc Gerrit-Change-Number: 43573 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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