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Hello,
Following patch extends the ROM decoding to last 1MB, allowing to use larger flashes such as SST49LF080A: 1024K x8 (8 Mbit)
Tested on my system, the flash is found and if I use coreboot in second half it works too.
Signed-off-by: Rudolf Marek r.marek@assembler.cz
Thanks, Rudolf
On 12.03.2008 23:43, Rudolf Marek wrote:
Hello,
Following patch extends the ROM decoding to last 1MB, allowing to use larger flashes such as SST49LF080A: 1024K x8 (8 Mbit)
Tested on my system, the flash is found and if I use coreboot in second half it works too.
Signed-off-by: Rudolf Marek r.marek@assembler.cz
Regardless of how/whether you address my comments below, this is Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Thanks, Rudolf
Regards, Carl-Daniel
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 3134) +++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (working copy) @@ -212,3 +212,18 @@ else PRINT_DEBUG("Done\r\n"); }
+void enable_rom_decode(void) +{
- device_t dev;
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID)
die("SB not found\r\n");
- /* ROM decode last 1MB FFC00000 - FFFFFFFF*/
Is it possible to decode more than the last 1MB and do we want to make this configurable?
- pci_write_config8(dev, 0x41, 0x7f);
+}
=================================================================== --- src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c (revision 3134) +++ src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c (working copy) @@ -192,6 +192,7 @@ w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init();
enable_rom_decode();
print_info("now booting... fallback\r\n");
@@ -207,6 +208,7 @@ /* Allow the HT devices to be found. */ enumerate_ht_chain();
Is the added newline above intentional?
/* Is this a deliberate reset by the BIOS? */ if (bios_reset_detected() && last_boot_normal_x) { goto normal_image;
On Wed, Mar 12, 2008 at 11:43:09PM +0100, Rudolf Marek wrote:
Following patch extends the ROM decoding to last 1MB, allowing to use larger flashes such as SST49LF080A: 1024K x8 (8 Mbit)
Tested on my system, the flash is found and if I use coreboot in second half it works too.
Signed-off-by: Rudolf Marek r.marek@assembler.cz
Acked-by: Uwe Hermann uwe@hermann-uwe.de
Tested on ASUS A8V-E Deluxe with a 1MB coreboot image (modified ROM_SIZE in targets/.../Config.lb) using a SST49LF080A chip. Boots fine.
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 3134) +++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (working copy) @@ -212,3 +212,18 @@ else PRINT_DEBUG("Done\r\n"); }
+void enable_rom_decode(void) +{
- device_t dev;
- /* Power management controller */
You mean "LPC" or maybe "Bus Control and Power Management" as per datasheet?
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID)
die("SB not found\r\n");
- /* ROM decode last 1MB FFC00000 - FFFFFFFF*/
Missing full stop and space before "*/".
Uwe.
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Hi all
Thanks for the comments. I fixed the newline and the comments. Only max 8mbit flashes are supported.
Committed revision 3148. Rudolf
On Sat, Mar 15, 2008 at 01:27:08AM +0100, Rudolf Marek wrote:
Only max 8mbit flashes are supported.
Is this a limit of 8237R?
//Peter
Peter Stuge wrote:
On Sat, Mar 15, 2008 at 01:27:08AM +0100, Rudolf Marek wrote:
Only max 8mbit flashes are supported.
Is this a limit of 8237R?
//Peter
There may be a way to extend the range from 1MB to the full range of 4MByte without hardware changes to a board.
There are some work-arounds that even allow the 8237r to access space beyond its 4MB "memory range". I'll be trying it out soon.
-Bari