#123: layout file -------------------------------------+-------------------------------------- Reporter: vivanov@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: v2 Keywords: layout address offset | Dependencies: Patchstatus: there is no patch | -------------------------------------+-------------------------------------- Hello,
I am trying to update the BIOS "ST M50FW080" and get the following incomprehensibility - layout file works in a strange way 1) saved the current BIOS
{{{ $ flashrom --read flash18_saved.rom }}}
2) then I filled first 512K of this file with zeros (it is needed because new BIOS will have 512K size) 3) then I created rom.layout file to use the normal image only:
{{{ 00000000:0007ffff stuff 00080000:000fffff normal }}}
4) and started to upgrade BIOS
{{{ $ flashrom --write --layout rom.layout --image flash18_saved.rom }}}
And get the following:
{{{ Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED '''0007 at address: 0x00070000DONE BLOCK 0x70000''' 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED }}}
'''Next'''
I changed the rom.layout file like follows:
{{{ # cat rom.layout 00000000:00080000 stuff 00080000:000fffff normal }}}
and get the '''right''' behaviour:
{{{ # flashrom --write --layout rom.layout --image normal --verify flash18_saved.rom Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED 0007 at address: 0x00070000SKIPPED 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED
Verifying flash... VERIFIED. }}}
Please explain me which rom layout I should use to update the last 512K of 1M BIOS?
On Wed, 04 Mar 2009 10:54:42 -0000, "coreboot" svn@coreboot.org wrote:
#123: layout file
-------------------------------------+--------------------------------------
Reporter: vivanov@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: v2 Keywords: layout address offset | Dependencies: Patchstatus: there is no patch |
-------------------------------------+--------------------------------------
Hello,
I am trying to update the BIOS "ST M50FW080" and get the following incomprehensibility - layout file works in a strange way
- saved the current BIOS
{{{ $ flashrom --read flash18_saved.rom }}}
- then I filled first 512K of this file with zeros (it is needed
because new BIOS will have 512K size) 3) then I created rom.layout file to use the normal image only:
{{{ 00000000:0007ffff stuff 00080000:000fffff normal }}}
- and started to upgrade BIOS
{{{ $ flashrom --write --layout rom.layout --image flash18_saved.rom }}}
And get the following:
{{{ Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED '''0007 at address: 0x00070000DONE BLOCK 0x70000''' 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED }}}
'''Next'''
I changed the rom.layout file like follows:
{{{ # cat rom.layout 00000000:00080000 stuff 00080000:000fffff normal }}}
and get the '''right''' behaviour:
{{{ # flashrom --write --layout rom.layout --image normal --verify flash18_saved.rom Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom@coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED 0007 at address: 0x00070000SKIPPED 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED
Verifying flash... VERIFIED. }}}
Please explain me which rom layout I should use to update the last 512K of 1M BIOS?
I don't get it? The M50FW080 is a 1024k chip? Why just flash the last 512k? If your trying to flash a 512k image to a 1024k chip just make your image 1024k by "cat 512k.bin 512k.bin > 1024k.bin". Start with a fresh flash by erasing your chip first, then flash it.
#123: layout file -------------------------------------+-------------------------------------- Reporter: vivanov@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: v2 Keywords: layout address offset | Dependencies: Patchstatus: there is no patch | -------------------------------------+--------------------------------------
Comment(by hailfinger):
Sorry I didn't see your bug report earlier. The bug you reported has been found independently by a source code analysis and is now fixed in latest svn.
Please retest. Thanks.
#123: layout file --------------------------------+------------------------------------------- Reporter: vivanov@… | Owner: somebody Type: defect | Status: closed Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: v2 Resolution: fixed | Keywords: layout address offset Dependencies: | Patchstatus: there is no patch --------------------------------+------------------------------------------- Changes (by hailfinger):
* status: new => closed * resolution: => fixed
-
coreboot -
Joseph Smith