r3147 - trunk/coreboot-v2/src/southbridge/via/k8t890

Author: ruik
Date: 2008-03-15 01:19:34 +0100 (Sat, 15 Mar 2008)
New Revision: 3147

Modified:
   trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c
Log:
Following patch fixes the retrain/reset sequence which caused problem with some
nVidia cards. The enable link should be enough, retrain is done there.

Tested on my system.

Signed-off-by: Rudolf Marek 
Acked-by: Uwe Hermann

Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c	2008-03-14 23:55:58 UTC (rev 3146)
+++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c	2008-03-15 00:19:34 UTC (rev 3147)
@@ -41,8 +41,6 @@
     * pci_write_config8(dev, 0xe2, 0x0);
     * pci_write_config8(dev, 0xe3, 0x92);
     */
-	/* Disable scrambling bit 6 to 1. */
-	pci_write_config8(dev, 0xc0, 0x43);

/* Set replay timer limit. */
    pci_write_config8(dev, 0xb1, 0xf0);
@@ -62,18 +60,6 @@
    reg = pci_read_config8(dev, 0x50);
    pci_write_config8(dev, 0x50, reg & ~0x10);

-	/* Retrain link. */
-	reg = pci_read_config8(dev, 0x50);
-	pci_write_config8(dev, 0x50, reg | 0x20);
-
-	reg = pci_read_config8(dev, 0x3e);
-	reg |= 0x40;		/* Bus reset. */
-	pci_write_config8(dev, 0x3e, reg);
-
-	reg = pci_read_config8(dev, 0x3e);
-	reg &= ~0x40;		/* Clear reset. */
-	pci_write_config8(dev, 0x3e, reg);
-
    dump_south(dev);
 }

@@ -97,18 +83,6 @@
    reg = pci_read_config8(dev, 0x50);
    pci_write_config8(dev, 0x50, reg & ~0x10);

-	/* Retrain. */
-	reg = pci_read_config8(dev, 0x50);
-	pci_write_config8(dev, 0x50, reg | 0x20);
-
-	reg = pci_read_config8(dev, 0x3e);
-	reg |= 0x40;		/* Bus reset. */
-	pci_write_config8(dev, 0x3e, reg);
-
-	reg = pci_read_config8(dev, 0x3e);
-	reg &= ~0x40;		/* Clear reset. */
-	pci_write_config8(dev, 0x3e, reg);
-
    dump_south(dev);
 }