[RFC] use of SMM with SSE/MMX...

[Rudolf Marek]

Hi all,

The MMX/SSE/x87 is not handled in save state map. GCC might produce such 
instructions if it wants.

Problem is what to do with that. Either we can compile all SMM code with 
-no-sse/mmx/fpu switches (I think those exists) or we could use the 
FXSAVE/FRSTORE instructions to backup the state. problem is that it needs 512 
bytes / CPU. Either could put that on stack which is 0x400 bytes total and make 
it 2 times smaller or for AMD we have 0x200 bytes still free in the save state 
map, but not on Intel.

Ideas?

Thanks
Rudolf

[Patrick Georgi]

Am Samstag, 2. Juli 2011 17:29:04, Rudolf Marek schrieb:
> Problem is what to do with that. Either we can compile all SMM code with
> -no-sse/mmx/fpu switches (I think those exists) or we could use the

To avoid future register additions to mess up things, what about 
-mcpu=i386 or something like that?

[Rudolf Marek]

Hi,

Yes even 486 would be good fit! (It has more closer aligns etc). As Stefan 
mentioned, some CPU might not have SSE enabled failing to execute coreboot. 
Maybe this is a bit broader problem.

Thanks
Rudolf

[Stefan Reinauer]

On 7/2/11 2:08 PM, Rudolf Marek wrote:
> Hi,
>
> Yes even 486 would be good fit! (It has more closer aligns etc). As 
> Stefan mentioned, some CPU might not have SSE enabled failing to 
> execute coreboot. Maybe this is a bit broader problem.
>
> Thanks
> Rudolf

Note that this problem does not happen with the reference toolchain that 
is i386-elf.

I agree, we should add CFLAGS to not compile coreboot or at least the 
SMM handler with MMX/SSE/... instructions.
There is no big gain in doing so anyways.

Stefan

[Scott Duplichan]

Stefan Reinauer wrote:

]On 7/2/11 2:08 PM, Rudolf Marek wrote:
]> Hi,
]>
]> Yes even 486 would be good fit! (It has more closer aligns etc). As 
]> Stefan mentioned, some CPU might not have SSE enabled failing to 
]> execute coreboot. Maybe this is a bit broader problem.
]>
]> Thanks
]> Rudolf
]>
]Note that this problem does not happen with the reference toolchain that 
]is i386-elf.

The asrock e350m1 project ends up with some mmx and xmm register usage,
at least as I build it. Some is forced in by the memory initialization
code. Examples are the asm code in function _mm_stream_si128_fs2() and
in file cache_as_ram.inc. In other cases, it appears the compiler
chooses these registers on its own. For the AMD reference code, this is
not surprising due to the use of compiler flags -march=k8-sse3 and
-mtune=k8-sse3. However, there are cases in common coreboot code where
xmm register accesses are generated, such as in coreboot_table.c.

]I agree, we should add CFLAGS to not compile coreboot or at least the 
]SMM handler with MMX/SSE/... instructions.
]There is no big gain in doing so anyways.

If the smm code is stand-alone and does not call library functions, then
using separate compile flags for it should be easy.

]Stefan