Author: stuge Date: Sat Feb 5 13:26:07 2011 New Revision: 6333 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6333
Log: Add PC87392 support
This adds support for the NSC PC87392 Super I/O. It is used in Lenovo Docking Stations as Super I/O chip.
v2 because of:
- skip some empty files - missing newlines in Kconfig and Makefile.inc - add the Kconfig option in sorted order
Thanks to idwer on irc for pointing that out.
Signed-off-by: Sven Schnelle svens@stackframe.org Acked-by: Peter Stuge peter@stuge.se
Added: trunk/src/superio/nsc/pc87392/ trunk/src/superio/nsc/pc87392/Makefile.inc trunk/src/superio/nsc/pc87392/chip.h trunk/src/superio/nsc/pc87392/early_serial.c trunk/src/superio/nsc/pc87392/pc87392.h trunk/src/superio/nsc/pc87392/superio.c Modified: trunk/src/superio/nsc/Kconfig trunk/src/superio/nsc/Makefile.inc
Modified: trunk/src/superio/nsc/Kconfig ============================================================================== --- trunk/src/superio/nsc/Kconfig Sat Feb 5 13:20:23 2011 (r6332) +++ trunk/src/superio/nsc/Kconfig Sat Feb 5 13:26:07 2011 (r6333) @@ -28,6 +28,8 @@ bool config SUPERIO_NSC_PC87366 bool +config SUPERIO_NSC_PC87392 + bool config SUPERIO_NSC_PC87417 bool config SUPERIO_NSC_PC87427
Modified: trunk/src/superio/nsc/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/Makefile.inc Sat Feb 5 13:20:23 2011 (r6332) +++ trunk/src/superio/nsc/Makefile.inc Sat Feb 5 13:26:07 2011 (r6333) @@ -23,6 +23,7 @@ subdirs-y += pc87360 subdirs-y += pc87366 subdirs-y += pc87382 +subdirs-y += pc87392 subdirs-y += pc87417 subdirs-y += pc87427 subdirs-y += pc97307
Added: trunk/src/superio/nsc/pc87392/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87392/Makefile.inc Sat Feb 5 13:26:07 2011 (r6333) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Sven Schnelle svens@stackframe.org +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NSC_PC87392) += superio.c +
Added: trunk/src/superio/nsc/pc87392/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87392/chip.h Sat Feb 5 13:26:07 2011 (r6333) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NSC_PC87392_CHIP_H +#define SUPERIO_NSC_PC87392_CHIP_H + +extern struct chip_operations superio_nsc_pc87392_ops; + +#include <uart8250.h> + +struct superio_nsc_pc87392_config { + struct uart8250 com1, com2; +}; + +#endif
Added: trunk/src/superio/nsc/pc87392/early_serial.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87392/early_serial.c Sat Feb 5 13:26:07 2011 (r6333) @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/romcc_io.h> +#include "pc87392.h" + +static void pc87392_enable_serial(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +}
Added: trunk/src/superio/nsc/pc87392/pc87392.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87392/pc87392.h Sat Feb 5 13:26:07 2011 (r6333) @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NSC_PC87392_H +#define SUPERIO_NSC_PC87392_H + +#define PC87392_FDC 0x00 +#define PC87392_PP 0x01 +#define PC87392_SP2 0x02 +#define PC87392_SP1 0x03 +#define PC87392_GPIO 0x07 +#define PC87392_WDT 0x0A + +#endif
Added: trunk/src/superio/nsc/pc87392/superio.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87392/superio.c Sat Feb 5 13:26:07 2011 (r6333) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <stdlib.h> +#include "chip.h" +#include "pc87392.h" + +static void init(device_t dev) +{ + struct superio_nsc_pc87392_config *conf = dev->chip_info; + struct resource *res0; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case PC87392_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + + case PC87392_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0} }, + { &ops, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} }, + { &ops, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0} }, + { &ops, PC87392_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0} }, + { &ops, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0} }, + { &ops, PC87392_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0} }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nsc_pc87392_ops = { + CHIP_NAME("NSC PC87392 Super I/O") + .enable_dev = enable_dev, +};
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