Author: uwe Date: Sat Jan 1 19:40:02 2011 New Revision: 6233 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6233
Log: AMD Bimini: Small fixes, and updates to recent trunk conventions.
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed to HAVE_DEBUG_CAR in r5898.
- Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.
- Drop obsolete/unused COMPRESS, see r6145.
- Drop obsolete SET_NB_CFG_54, see r6086.
- Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077. Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.
- Rename some GENERATE_* options to HAVE_*, see r6027.
- Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.
- Drop ACPI_SSDTX_NUM, the global default is 0 already.
- Random whitespace and coding style fixes.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/mainboard/amd/bimini_fam10/Kconfig trunk/src/mainboard/amd/bimini_fam10/chip.h trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c trunk/src/mainboard/amd/bimini_fam10/irq_tables.c trunk/src/mainboard/amd/bimini_fam10/mainboard.c trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h trunk/src/mainboard/amd/bimini_fam10/mptable.c trunk/src/mainboard/amd/bimini_fam10/pmio.c trunk/src/mainboard/amd/bimini_fam10/pmio.h trunk/src/mainboard/amd/bimini_fam10/reset.c trunk/src/mainboard/amd/bimini_fam10/resourcemap.c trunk/src/mainboard/amd/bimini_fam10/romstage.c
Modified: trunk/src/mainboard/amd/bimini_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/Kconfig Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/Kconfig Sat Jan 1 19:40:02 2011 (r6233) @@ -6,7 +6,9 @@ select CPU_AMD_SOCKET_ASB2 select DIMM_DDR3 select DIMM_REGISTERED - #select QRANK_DIMM_SUPPORT + # TODO: Enable QRANK_DIMM_SUPPORT? Was commented in the Kconfig file, + # but enabled in the romstage.c file. + select QRANK_DIMM_SUPPORT select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 @@ -14,21 +16,22 @@ select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE - select GENERATE_PIRQ_TABLE - select GENERATE_MP_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select CACHE_AS_RAM select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT select AMDMCT - select GENERATE_ACPI_TABLES + select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA + select HAVE_DEBUG_CAR + select SET_FIDVID
config MAINBOARD_DIR string @@ -90,10 +93,6 @@ hex default 0xc0000
-config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 @@ -106,8 +105,4 @@ hex default 0x200000
-config COMPRESS - hex - default 0 - endif #BOARD_AMD_BIMINI_FAM10
Modified: trunk/src/mainboard/amd/bimini_fam10/chip.h ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/chip.h Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/chip.h Sat Jan 1 19:40:02 2011 (r6233) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
- extern struct chip_operations mainboard_ops;
struct mainboard_config {};
Modified: trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/get_bus_conf.c Sat Jan 1 19:40:02 2011 (r6233) @@ -26,7 +26,6 @@ #if CONFIG_LOGICAL_CPUS==1 #include <cpu/amd/multicore.h> #endif - #include <cpu/amd/amdfam10_sysconf.h>
/* Global variables for MB layouts and these will be shared by irqtable mptable
Modified: trunk/src/mainboard/amd/bimini_fam10/irq_tables.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/irq_tables.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/irq_tables.c Sat Jan 1 19:40:02 2011 (r6233) @@ -22,10 +22,8 @@ #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> - #include <cpu/amd/amdfam10_sysconf.h>
- static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, @@ -44,6 +42,7 @@ pirq_info->slot = slot; pirq_info->rfu = rfu; } + extern u8 bus_isa; extern u8 bus_rs780[8]; extern u8 bus_sb800[2];
Modified: trunk/src/mainboard/amd/bimini_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/mainboard.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/mainboard.c Sat Jan 1 19:40:02 2011 (r6233) @@ -29,7 +29,6 @@ #include "pmio.h" #include "chip.h"
- uint64_t uma_memory_base, uma_memory_size;
u8 is_dev3_present(void); @@ -94,6 +93,7 @@ { return 0; } + #if 0 /* not tested yet. */ /******************************************************** * bimini uses SB800 GPIO9 to detect IDE_DMA66. @@ -195,6 +195,6 @@ }
struct chip_operations mainboard_ops = { - CHIP_NAME("AMD BIMINI Mainboard") + CHIP_NAME("AMD Bimini Mainboard") .enable_dev = bimini_enable, };
Modified: trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/mb_sysconf.h Sat Jan 1 19:40:02 2011 (r6233) @@ -18,7 +18,6 @@ */
#ifndef MB_SYSCONF_H - #define MB_SYSCONF_H
struct mb_sysconf_t { @@ -38,8 +37,7 @@ u32 sbdn3; u32 sbdn3a[31]; u32 sbdn5[31]; - u32 bus_type[256]; + u32 bus_type[256]; };
#endif -
Modified: trunk/src/mainboard/amd/bimini_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/mptable.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/mptable.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
- #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -25,15 +24,12 @@ #include <string.h> #include <stdint.h> #include "pmio.h" - #include <cpu/amd/amdfam10_sysconf.h>
extern int bus_isa; extern u8 bus_rs780[11]; extern u8 bus_sb800[2]; - extern u32 apicid_sb800; - extern u32 bus_type[256]; extern u32 sbdn_rs780; extern u32 sbdn_sb800;
Modified: trunk/src/mainboard/amd/bimini_fam10/pmio.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/pmio.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/pmio.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,8 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
- -#include <arch/io.h> /*inb, outb*/ +#include <arch/io.h> #include "pmio.h"
static void pmio_write_index(u16 port_base, u8 reg, u8 value) @@ -52,4 +51,3 @@ { return pmio_read_index(PM2_INDEX, reg); } -
Modified: trunk/src/mainboard/amd/bimini_fam10/pmio.h ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/pmio.h Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/pmio.h Sat Jan 1 19:40:02 2011 (r6233) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
- #ifndef _PMIO_H_ #define _PMIO_H_
Modified: trunk/src/mainboard/amd/bimini_fam10/reset.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/reset.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/reset.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,10 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
- #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ +#include <arch/io.h> +#include <arch/romcc_io.h>
#define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) @@ -33,13 +32,12 @@
static inline void set_bios_reset(void) { - u32 nodes; - u32 htic; + u32 nodes, htic; device_t dev; int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; @@ -63,4 +61,3 @@ /* link reset */ outb(0x06, 0x0cf9); } -
Modified: trunk/src/mainboard/amd/bimini_fam10/resourcemap.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/resourcemap.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/resourcemap.c Sat Jan 1 19:40:02 2011 (r6233) @@ -17,8 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
- - static void setup_mb_resource_map(void) { static const unsigned int register_values[] = { @@ -278,4 +276,3 @@ max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); } -
Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/romstage.c Sat Jan 1 19:10:07 2011 (r6232) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Sat Jan 1 19:40:02 2011 (r6233) @@ -21,21 +21,10 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1 - -#define SET_NB_CFG_54 1 - -//used by raminit -#define QRANK_DIMM_SUPPORT 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -48,47 +37,36 @@ #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - #include <console/loglevel.h> #include "cpu/x86/bist.h" - #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" - #include "southbridge/amd/rs780/early_setup.c" #include <SbEarly.h> #include <SBPLATFORM.h> /* SB OEM constants */ #include <sb800_smbus.h> #include "northbridge/amd/amdfam10/debug.c"
- static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { - int result; - result = do_smbus_read_byte(SMBUS_IO_BASE, device, address); - return result; + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); }
- #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" - #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - #include "northbridge/amd/amdfam10/early_ht.c"
#define RC00 0 @@ -110,11 +88,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -183,20 +159,20 @@ */ wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); - #endif +#endif
post_code(0x38);
/* run _early_setup before soft-reset. */ rs780_early_setup();
- #if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
-
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