5 May
2004
5 May
'04
1:24 p.m.
If I changed config.lb
PCI 1:0.2 on --> PCI 1:0.2 off
The PCI 1:0.0 and PCI 1:0.1 will be disabled together.
According to AMD 8111 data sheet, LPC 0x48, only can be disabled the device
in second bus by device num, and the three USB share one device number.
So I guess the code about 0x47 must be there.
YH
-----邮件原件-----
发件人: ron minnich [mailto:rminnich@lanl.gov]
发送时间: 2004年5月5日 9:28
收件人: YhLu
抄送: Stefan Reinauer; linuxbios(a)clustermatic.org
主题: Re: 答复: 答复: Disable USB2 in AMD8111 and remove ide hardcode io
addr
On Wed, 5 May 2004, YhLu wrote:
I change my mind, disable that in Config.lb is better
and less code.
good!
ron
5 May
5 May
2:07 p.m.
On Wed, 5 May 2004, YhLu wrote:
If I changed config.lb
PCI 1:0.2 on --> PCI 1:0.2 off
The PCI 1:0.0 and PCI 1:0.1 will be disabled together.
According to AMD 8111 data sheet, LPC 0x48, only can be disabled the device
in second bus by device num, and the three USB share one device number.
So I guess the code about 0x47 must be there.
sounds ok.
ron
2:12 p.m.
New subject: 答复: 答复: 答复: Disable USB2 in AMD8111 and remove ide hardcode io addr
On Wed, 2004-05-05 at 10:51, YhLu wrote:
If I changed config.lb
PCI 1:0.2 on --> PCI 1:0.2 off
The PCI 1:0.0 and PCI 1:0.1 will be disabled together.
According to AMD 8111 data sheet, LPC 0x48, only can be disabled the device
in second bus by device num, and the three USB share one device number.
So I guess the code about 0x47 must be there.
Ron and I just dicurssed about the enable/disable mechanism for
amd8111. We are going to implement a slightly better one soon.
Actually, the enable/disable for devices in amd8111 is multiplexed
in amd8111_enable and the device_operation::enable() is directed to
amd8111_enable. We are going to demultiplex this and each devices
has its own "real" enable method.
Ollie
6:52 p.m.
New subject: ��: ��: ��: Disable USB2 in AMD8111 and remove ide hardcode io addr
Li-Ta Lo <ollie(a)lanl.gov> writes:
On Wed, 2004-05-05 at 10:51, YhLu wrote:
No. This must be per chip.
Because you cannot necessarily see these devices before you enable/disable
them. And only one device on the 8111 actually does the enable/disable.
Eric
If I changed config.lb
PCI 1:0.2 on --> PCI 1:0.2 off
The PCI 1:0.0 and PCI 1:0.1 will be disabled together.
According to AMD 8111 data sheet, LPC 0x48, only can be disabled the device
in second bus by device num, and the three USB share one device number.
So I guess the code about 0x47 must be there.
Ron and I just dicurssed about the enable/disable mechanism for
amd8111. We are going to implement a slightly better one soon.
Actually, the enable/disable for devices in amd8111 is multiplexed
in amd8111_enable and the device_operation::enable() is directed to
amd8111_enable. We are going to demultiplex this and each devices
has its own "real" enable method.
7:30 p.m.
New subject: çå¤: çå¤: çå¤: Disable USB2 in AMD8111 and remove ide hardcode io addr
On Wed, 2004-05-05 at 16:12, Eric W. Biederman wrote:
Li-Ta Lo <ollie(a)lanl.gov> writes:
What do you mean ? Do you mean when I try to enable/disable something on
8111 but the LPC bridge is not there yet ?
On Wed, 2004-05-05 at 10:51, YhLu wrote:
No. This must be per chip.
Because you cannot necessarily see these devices before you enable/disable If I changed config.lb
PCI 1:0.2 on --> PCI 1:0.2 off
The PCI 1:0.0 and PCI 1:0.1 will be disabled together.
According to AMD 8111 data sheet, LPC 0x48, only can be disabled the device
in second bus by device num, and the three USB share one device number.
So I guess the code about 0x47 must be there.
Ron and I just dicurssed about the enable/disable mechanism for
amd8111. We are going to implement a slightly better one soon.
Actually, the enable/disable for devices in amd8111 is multiplexed
in amd8111_enable and the device_operation::enable() is directed to
amd8111_enable. We are going to demultiplex this and each devices
has its own "real" enable method. them. And only one device on the 8111 actually does
the enable/disable.
The function amd8111_enable() is used both as .enable and .enable_dev.
Why are you doing this ? This make it very difficult know under which
contex the function is called and what it is supposed to do when it acts
as different method.
What I want to do is make amd8111_enable() a generic public function and
each device's .enable() calls amd8111_enable() to do the real thing.
Ollie
7:35 p.m.
New subject: çå¤: çå¤: çå¤: Disable USB2 in AMD8111 and remove ide hardcode io addr
On Wed, 2004-05-05 at 16:12, Eric W. Biederman wrote:
No. This must be per chip.
Because you cannot necessarily see these devices before you enable/disable
them. And only one device on the 8111 actually does the enable/disable.
BTW, as shown in the log, the amd8111_enable is called as .enable and
.enable_dev multiple times for some specific device. Is that what we
want ? Why you want to enable/disable the same device so many times ?
Ollie
PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003
amd8111_enable_dev: enabling PCI: 01:00.0 [1022/7460]
PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007
HyperT reset not needed
PCI: pci_scan_bus for bus 1
POST: 0x24
PCI: 01:01.0 [1022/7450] bus ops
PCI: 01:01.0 [1022/7450] enabled
PCI: 01:01.1 [1022/7451] ops
PCI: 01:01.1 [1022/7451] enabled
PCI: 01:02.0 [1022/7450] bus ops
PCI: 01:02.0 [1022/7450] enabled
PCI: 01:02.1 [1022/7451] ops
PCI: 01:02.1 [1022/7451] enabled
amd8111_enable_dev: enabling PCI: 01:03.0 [1022/7460]
PCI: 01:03.0 [1022/7460] bus ops
amd8111_enable_dev: enabling PCI: 01:03.0 [1022/7460]
PCI: 01:03.0 [1022/7460] enabled
amd8111_enable_dev: enabling PCI: 01:04.0 [1022/7468]
PCI: 01:04.0 [1022/7468] bus ops
amd8111_enable: enabling PCI: 01:04.0 [1022/7468]
PCI: 01:04.0 [1022/7468] enabled
amd8111_enable_dev: enabling PCI: 01:04.1 [1022/7469]
PCI: 01:04.1 [1022/7469] ops
amd8111_enable_dev: enabling PCI: 01:04.1 [1022/7469]
PCI: 01:04.1 [1022/7469] enabled
amd8111_enable_dev: enabling PCI: 01:04.2 [1022/746a]
amd8111_enable_dev: enabling PCI: 01:04.2 [1022/746a]
PCI: 01:04.2 [1022/746a] enabled
amd8111_enable_dev: enabling PCI: 01:04.3 [1022/746b]
PCI: 01:04.3 [1022/746b] ops
amd8111_enable: enabling PCI: 01:04.3 [1022/746b]
PCI: 01:04.3 [1022/746b] enabled
amd8111_enable_dev: enabling PCI: 01:04.5 [1022/746d]
PCI: 01:04.5 [1022/746d] ops
amd8111_enable: disabling PCI: 01:04.5 [1022/746d]
PCI: 01:04.5 [1022/746d] disabled
amd8111_enable_dev: enabling PCI: 01:04.6 [1022/746e]
PCI: 01:04.6 [1022/746e] ops
amd8111_enable: disabling PCI: 01:04.6 [1022/746e]
PCI: 01:04.6 [1022/746e] disabled
POST: 0x25
PCI: pci_scan_bus for bus 2
POST: 0x24
PCI: 02:01.0 [14e4/1648] enabled
PCI: 02:01.1 [14e4/1648] enabled
PCI: 02:02.0 [1000/0030] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=02
POST: 0x55
PCI: pci_scan_bus for bus 3
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=03
POST: 0x55
PCI: pci_scan_bus for bus 4
POST: 0x24
amd8111_enable_dev: enabling PCI: 04:00.0 [1022/7464]
PCI: 04:00.0 [1022/7464] ops
amd8111_enable: enabling PCI: 04:00.0 [1022/7464]
PCI: 04:00.0 [1022/7464] enabled
amd8111_enable_dev: enabling PCI: 04:00.1 [1022/7464]
PCI: 04:00.1 [1022/7464] ops
amd8111_enable: enabling PCI: 04:00.1 [1022/7464]
PCI: 04:00.1 [1022/7464] enabled
amd8111_enable_dev: enabling PCI: 04:00.2 [1022/7463]
PCI: 04:00.2 [1022/7463] ops
amd8111_enable: enabling PCI: 04:00.2 [1022/7463]
PCI: 04:00.2 [1022/7463] enabled
amd8111_enable_dev: enabling PCI: 04:01.0 [1022/7462]
PCI: 04:01.0 [1022/7462] ops
amd8111_enable: disabling PCI: 04:01.0 [1022/7462]
6107
days inactive
6107
days old
5 comments
4 participants
participants (4)
-
ebiederman＠lnxi.com -
Li-Ta Lo -
ron minnich -
YhLu