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I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS...
Unfortunately I do not have any other DDR3 modules to test.
Best regards,
n3ph
On 05/20/15 19:20, Vadim Bendebury wrote:
SPD is some data saved on the memory module, available to the processor to read to find out memory properies. These data are protected by a check code (CRC) which allows the CPU to verify that it read the data correctly. Apparently this check is failing in your case.
Some likely reasons could be a noisy i2c interface (used to read SPD) or someone writing the SPD storage on memory module(s) and corrupteding it.
--vb
On Wed, May 20, 2015 at 8:51 AM, Michael Gerlach n3ph@terminal21.de wrote: Hi all,
i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like there are some issues regarding the size of the modules..
Best regards,
n3ph
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
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On 05/20/2015 12:46 PM, Michael Gerlach wrote:
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I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS...
Unfortunately I do not have any other DDR3 modules to test.
Best regards,
n3ph
It is possible the vendor BIOS ignores the checksum. Is there any way to get a dump of the SPD contents while running Linux (e.g. via decode-dimms)?
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Hi!
I added debug statements (http://pastebin.com/iSFstXmv) and realized that the calculated checksum is 0..
CLC_CRC : 0 SPD_CRC : ce66
Furthermore I had a look at src/device/dram/ddr3.c line 155 - The capacity is given with 4GB (as you see in the log) but the dram_print_spd_ddr3 output from dimm->size_mb is 8192MB O_o
The first log was from a quite out-dated build - I reseted on 4679c41db292b80ce51c7d923e2f22258145522b..
- -> http://pastebin.com/Xxq0Lwyp
Best regards,
n3ph
On 05/20/15 21:03, Timothy Pearson wrote:
On 05/20/2015 12:46 PM, Michael Gerlach wrote:
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I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS...
Unfortunately I do not have any other DDR3 modules to test.
Best regards,
n3ph
It is possible the vendor BIOS ignores the checksum. Is there any way to get a dump of the SPD contents while running Linux (e.g. via decode-dimms)?
- -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard
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I forgot to mention that somehow the ram frequency is not detected correctly...
PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency No lock frequency found
Here is the output from dmidecode -t 17:
# dmidecode 2.12 # SMBIOS entry point at 0xdaa9e000 SMBIOS 2.7 present.
Handle 0x0008, DMI type 17, 34 bytes Memory Device Array Handle: 0x0007 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 8192 MB Form Factor: SODIMM Set: None Locator: ChannelA-DIMM0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Kingston Serial Number: 302A9F79 Asset Tag: None Part Number: 9905428-095.D00LF Rank: Unknown Configured Clock Speed: 1600 MHz
Handle 0x0009, DMI type 17, 34 bytes Memory Device Array Handle: 0x0007 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 8192 MB Form Factor: SODIMM Set: None Locator: ChannelB-DIMM0 Bank Locator: BANK 2 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Kingston Serial Number: 322A201D Asset Tag: None Part Number: 9905428-095.D00LF Rank: Unknown Configured Clock Speed: 1600 MHz
best regards,
n3ph
On 05/20/15 21:03, Timothy Pearson wrote:
On 05/20/2015 12:46 PM, Michael Gerlach wrote:
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I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS...
Unfortunately I do not have any other DDR3 modules to test.
Best regards,
n3ph
It is possible the vendor BIOS ignores the checksum. Is there any way to get a dump of the SPD contents while running Linux (e.g. via decode-dimms)?
- -- Bitte benutzt GPG: http://de.wikipedia.org/wiki/GNU_Privacy_Guard
On Wed, May 20, 2015 at 1:13 PM, Michael Gerlach n3ph@terminal21.de wrote:
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I forgot to mention that somehow the ram frequency is not detected correctly...
PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency No lock frequency found
The SPD data should be read via SMBus long before PLL locking for the DRAM itself takes place.
If you're unable to successfully read the SPDs, then it makes sense that later init would fail.
-
David Hendricks -
Michael Gerlach -
Timothy Pearson