r967 - in coreboot-v3: include/device mainboard mainboard/jetway mainboard/jetway/j7f2 northbridge/via/cn700 southbridge/via/vt8237 superio/fintek/f71805f
Author: rminnich Date: 2008-10-31 19:13:20 +0100 (Fri, 31 Oct 2008) New Revision: 967 Added: coreboot-v3/mainboard/jetway/ coreboot-v3/mainboard/jetway/Kconfig coreboot-v3/mainboard/jetway/j7f2/ coreboot-v3/mainboard/jetway/j7f2/Makefile coreboot-v3/mainboard/jetway/j7f2/cmos.layout coreboot-v3/mainboard/jetway/j7f2/dts coreboot-v3/mainboard/jetway/j7f2/initram.c coreboot-v3/mainboard/jetway/j7f2/mainboard.c coreboot-v3/mainboard/jetway/j7f2/mainboard.h coreboot-v3/mainboard/jetway/j7f2/stage1.c coreboot-v3/northbridge/via/cn700/agp.c coreboot-v3/northbridge/via/cn700/memctrl.c coreboot-v3/northbridge/via/cn700/pci.c coreboot-v3/northbridge/via/cn700/stage2.c coreboot-v3/northbridge/via/cn700/stage2.h coreboot-v3/northbridge/via/cn700/vga.c coreboot-v3/southbridge/via/vt8237/ide.c coreboot-v3/southbridge/via/vt8237/ide.dts coreboot-v3/southbridge/via/vt8237/lpc.c coreboot-v3/southbridge/via/vt8237/lpc.dts coreboot-v3/southbridge/via/vt8237/sata.c coreboot-v3/southbridge/via/vt8237/sata.dts coreboot-v3/southbridge/via/vt8237/vt8237.c Modified: coreboot-v3/include/device/pci_ids.h coreboot-v3/mainboard/Kconfig coreboot-v3/northbridge/via/cn700/Makefile coreboot-v3/northbridge/via/cn700/cn700.h coreboot-v3/southbridge/via/vt8237/Makefile coreboot-v3/southbridge/via/vt8237/stage1.c coreboot-v3/southbridge/via/vt8237/vt8237.h coreboot-v3/superio/fintek/f71805f/superio.c Log: via vt8237, cn700 and jetway j7f2. Does not yet build Acked-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Modified: coreboot-v3/include/device/pci_ids.h =================================================================== --- coreboot-v3/include/device/pci_ids.h 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/include/device/pci_ids.h 2008-10-31 18:13:20 UTC (rev 967) @@ -264,6 +264,14 @@ #define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B #define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_CN700_AGP 0x0314 +#define PCI_DEVICE_ID_VIA_CN700_ERR 0x1314 +#define PCI_DEVICE_ID_VIA_CN700_HOST 0x2314 +#define PCI_DEVICE_ID_VIA_CN700_MEMCTRL 0x3208 +#define PCI_DEVICE_ID_VIA_CN700_PM 0x4314 +#define PCI_DEVICE_ID_VIA_CN700_VLINK 0x7314 +#define PCI_DEVICE_ID_VIA_CN700_BRIDGE 0xB198 +#define PCI_DEVICE_ID_VIA_CN700_VGA 0x3344 #define PCI_DEVICE_ID_VIA_VT8237_EHCI 0x3104 #define PCI_DEVICE_ID_VIA_VT8237_LAN 0x3065 #define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227 @@ -272,7 +280,5 @@ #define PCI_DEVICE_ID_VIA_VT8237R_SATA 0x3149 #define PCI_DEVICE_ID_VIA_VT8237S_SATA 0x5372 #define PCI_DEVICE_ID_VIA_VT8237_UHCI 0x3038 -#define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e - #endif /* DEVICE_PCI_IDS_H */ Modified: coreboot-v3/mainboard/Kconfig =================================================================== --- coreboot-v3/mainboard/Kconfig 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/mainboard/Kconfig 2008-10-31 18:13:20 UTC (rev 967) @@ -53,6 +53,11 @@ help Select this option for various systems from GIGABYTE. +config VENDOR_JETWAY + bool "Jetway" + help + Select this option for systems from Jetway. + config VENDOR_EMULATION bool "Emulated systems" help @@ -76,6 +81,7 @@ source "mainboard/artecgroup/Kconfig" source "mainboard/emulation/Kconfig" source "mainboard/gigabyte/Kconfig" +source "mainboard/jetway/Kconfig" source "mainboard/pcengines/Kconfig" source "mainboard/via/Kconfig" Added: coreboot-v3/mainboard/jetway/Kconfig =================================================================== --- coreboot-v3/mainboard/jetway/Kconfig (rev 0) +++ coreboot-v3/mainboard/jetway/Kconfig 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,88 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_JETWAY + +config BOARD_JETWAY_J7F2 + bool "J7F2 Series (INCOMPLETE)" + depends CONFIG_EXPERIMENTAL + select ARCH_X86 + select CPU_VIA_C7 + select OPTION_TABLE + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237 + select SUPERIO_FINTEK_F71805F + help + Jetway J7F2-Series board. +endchoice + +##TODO: Make this more generic, perhaps put it in a per-NB Kconfig. This can't +## be completely universal, because different video chips support +## different video memory sizes. + +choice + prompt "Video Memory Size" + default CN700_VIDEO_MB_32 + depends NORTHBRIDGE_VIA_CN700 + +config CN700_VIDEO_MB_NONE + bool "none" + help + Choose this option to disable the onboard video. + +config CN700_VIDEO_MB_32 + bool "32 MB" + help + Choose this option to use 32MB of system memory for onboard video. + +config CN700_VIDEO_MB_64 + bool "64 MB" + help + Choose this option to use 64MB of system memory for onboard video. + +config CN700_VIDEO_MB_128 + bool "128 MB" + help + Choose this option to use 128MB of system memory for onboard video. + +config CN700_VIDEO_MB_256 + bool "256 MB" + help + Choose this option to use 256MB of system memory for onboard video. + + +config CN700_VIDEO_MB + int + default 0 if CN700_VIDEO_MB_NONE + default 32 if CN700_VIDEO_MB_32 + default 64 if CN700_VIDEO_MB_64 + default 128 if CN700_VIDEO_MB_128 + default 256 if CN700_VIDEO_MB_256 + help + Map the config names to an integer. + +endchoice + +config MAINBOARD_DIR + string + default jetway/j7f2 + depends BOARD_JETWAY_J7F2 + Added: coreboot-v3/mainboard/jetway/j7f2/Makefile =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/Makefile (rev 0) +++ coreboot-v3/mainboard/jetway/j7f2/Makefile 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,74 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## TODO + +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/arch/x86/stage1_mtrr.c + +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/via/cn700/initram.c \ + $(src)/southbridge/via/vt8237/stage1.c \ + $(src)/lib/ramtest.c \ + $(src)/arch/x86/pci_ops_conf1.c + +STAGE2_MAINBOARD_SRC = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## TODO + +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/arch/x86/stage1_mtrr.c + +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/via/cn700/initram.c \ + $(src)/southbridge/via/vt8237/stage1.c \ + $(src)/lib/ramtest.c \ + $(src)/arch/x86/pci_ops_conf1.c + +STAGE2_MAINBOARD_SRC = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Added: coreboot-v3/mainboard/jetway/j7f2/cmos.layout =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/cmos.layout (rev 0) +++ coreboot-v3/mainboard/jetway/j7f2/cmos.layout 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,98 @@ +entries + +# start-bit length config config-ID name +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +412 4 e 6 debug_level +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +# ID value text + +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 + +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +checksums + +checksum 392 1007 1008 + +entries + +# start-bit length config config-ID name +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +412 4 e 6 debug_level +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +# ID value text + +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 + +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +checksums + +checksum 392 1007 1008 + Added: coreboot-v3/mainboard/jetway/j7f2/dts =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/dts (rev 0) +++ coreboot-v3/mainboard/jetway/j7f2/dts 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,264 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +-[0000:00]-+-00.0 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.1 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.2 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.3 VIA Technologies, Inc. PT890 Host Bridge + +-00.4 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.7 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-01.0-[0000:01]----00.0 VIA Technologies, Inc. UniChrome Pro IGP + +-08.0 RaLink RT2561/RT61 802.11g PCI + +-0a.0 VIA Technologies, Inc. IEEE 1394 Host Controller + +-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller + +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE + +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.4 VIA Technologies, Inc. USB 2.0 + +-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] + +-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller + \-12.0 VIA Technologies, Inc. VT6102 [Rhine-II] +*/ + +/{ + mainboard_vendor = "Jetway"; + mainboard_name = "J7F2"; + mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */ + mainboard_pci_subsystem_device = "0xbeef"; /* TODO */ + cpus { }; + apic@0 { + }; + domain@0 { + pci@0,0 {}; + pci@0,1 {}; + pci@0,2 {}; + pci@0,3 {}; + pci@0,4 {}; + pci@0,7 {}; + pci@1,0 {}; + pci@f,0 {}; + pci@10,0 { + /config/("southbridge/via/vt8237/sata.dts"); + }; + pci@10,1 { + /config/("southbridge/via/vt8237/ide.dts"); + }; + pci@11,0 { + /config/("southbridge/via/vt8237/lpc.dts"); + }; + ioport@4e { + /config/("superio/fintek/f71805f/dts"); + com2enable = "1"; + }; + }; +}; +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +-[0000:00]-+-00.0 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.1 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.2 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.3 VIA Technologies, Inc. PT890 Host Bridge + +-00.4 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.7 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-01.0-[0000:01]----00.0 VIA Technologies, Inc. UniChrome Pro IGP + +-08.0 RaLink RT2561/RT61 802.11g PCI + +-0a.0 VIA Technologies, Inc. IEEE 1394 Host Controller + +-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller + +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE + +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.4 VIA Technologies, Inc. USB 2.0 + +-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] + +-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller + \-12.0 VIA Technologies, Inc. VT6102 [Rhine-II] +*/ + +/{ + mainboard_vendor = "Jetway"; + mainboard_name = "J7F2"; + mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */ + mainboard_pci_subsystem_device = "0xbeef"; /* TODO */ + cpus { }; + apic@0 { + }; + domain@0 { + pci@0,0 {}; + pci@0,1 {}; + pci@0,2 {}; + pci@0,3 {}; + pci@0,4 {}; + pci@0,7 {}; + pci@1,0 {}; + pci@f,0 {}; + pci@10,0 { + /config/("southbridge/via/vt8237/sata.dts"); + }; + pci@10,1 { + /config/("southbridge/via/vt8237/ide.dts"); + }; + pci@11,0 { + /config/("southbridge/via/vt8237/lpc.dts"); + }; + ioport@4e { + /config/("superio/fintek/f71805f/dts"); + com2enable = "1"; + }; + }; +}; +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +-[0000:00]-+-00.0 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.1 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.2 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.3 VIA Technologies, Inc. PT890 Host Bridge + +-00.4 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-00.7 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge + +-01.0-[0000:01]----00.0 VIA Technologies, Inc. UniChrome Pro IGP + +-08.0 RaLink RT2561/RT61 802.11g PCI + +-0a.0 VIA Technologies, Inc. IEEE 1394 Host Controller + +-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller + +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE + +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller + +-10.4 VIA Technologies, Inc. USB 2.0 + +-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] + +-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller + \-12.0 VIA Technologies, Inc. VT6102 [Rhine-II] + +Wow, almost identical to what I came up with, at least for the moment. The southbridge is vt8237@d11f0, it's connected to bus0 by via v-link (a modified version of pci, very similar to agp afaics), which is configured through d0f7 and d11f0. d8f0 is in the only pci slot, and daf0 is an optional feature that's not present on some boards. The northbridge doesn't have pci-e, d0f0 and d1f0 are agp, 1x/2x and 4x/8x respectively, we need to decide which should control the agp slot/onboard video (but I've never been able to find a board with an agp slot, and onboard video is always on d1f0). The d0f1 hanging off d1f0 is onboard video. d0f1 is a dummy device only for error reporting. the cpu is connected to d0f2, memory to d0f3, and d0f4 is a dummy device for more memory registers. d0f7 is, as I said, vlink control. + +If you need any more info, let me know. +Thanks! + +Ron sez: we need to show the tree with the 8237 in it hanging off some pci bus + */ + +/{ + device_operations="jetway"; + mainboard_vendor = "jetway"; + mainboard_name = "xyz"; + cpus { }; + apic@0 { + }; + domain@0 { + /config/("northbridge/via/cn700/bridge.dts"); + pci@0,1{ + /config/("northbridge/via/cn700/pcie.dts"); + }; + pci@0,2{ + /config/("northbridge/via/cn700/pcie2.dts"); + }; + pci@0,3{ + /config/("northbridge/via/cn700/pci.dts"); + }; + pci@0,4{ + /config/("northbridge/via/cn700/pcie3.dts"); + }; + pci@0,7{ + /config/("northbridge/via/cn700/pcie4.dts"); + }; + pci@1,0{ + /config/("northbridge/via/cn700/igp.dts"); + }; + pci@8,0{ + /config/("northbridge/via/ieee80211.dts"); + }; + pci@a,0{ + /config/("northbridge/via/ieee1394.dts"); + }; + pci@f,0{ + /config/("northbridge/via/sata.dts"); + }; + pci@f,1{ + /config/("northbridge/via/ide.dts"); + }; + pci@10,0{ + /config/("northbridge/via/usb0.dts"); + }; + pci@10,0{ + /config/("northbridge/via/usb1.dts"); + }; + pci@10,1{ + /config/("northbridge/via/usb2.dts"); + }; + pci@10,2{ + /config/("northbridge/via/usb3.dts"); + }; + pci@10,3{ + /config/("northbridge/via/us4.dts"); + }; + pci@10,4{ + /config/("northbridge/via/usb20.dts"); + }; + pci@11,0{ + /config/("northbridge/via/isa.dts"); + }; + pci@11,5{ + /config/("northbridge/via/ac97.dts"); + }; + pci@12,0{ + /config/("northbridge/via/rhine.dts"); + }; + }; +}; Added: coreboot-v3/mainboard/jetway/j7f2/initram.c =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/initram.c (rev 0) +++ coreboot-v3/mainboard/jetway/j7f2/initram.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,426 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <io.h> +#include <spd.h> +#include <via_c7.h> +#include <arch/x86/pci_ops.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <superio/fintek/f71805f/f71805f.h> +#include <southbridge/via/vt8237/vt8237.h> +#include <northbridge/via/cn700/cn700.h> + +#define SMBUS_IO_BASE 0x0400 + +u8 spd_read_byte(u16 dev, u8 addr) +{ + return smbus_read_byte(dev, addr, SMBUS_IO_BASE); +} + +void find_smbus_devices(u8 min, u8 max) +{ + u8 dev; + u8 result; + for(dev = min; dev < max; dev++) + { + result = spd_read_byte(dev, SPD_MEMORY_TYPE); + switch(result) + { + case SPD_MEMORY_TYPE_SDRAM: printk(BIOS_DEBUG, + "Possible SDRAM spd at address 0x%2x\n", dev); + break; + case SPD_MEMORY_TYPE_SDRAM_DDR: printk(BIOS_DEBUG, + "Possible DDR SDRAM spd at address 0x%2x\n", dev); + break; + case SPD_MEMORY_TYPE_SDRAM_DDR2: printk(BIOS_DEBUG, + "Possible DDR2 SDRAM spd at address 0x%2x\n", dev); + break; + }; + } +} + + +void dump_smbus_registers(void) +{ + int device; + for(device = 1; device < (int)0x80; device++) { + int j; + //if(spd_read_byte(device, 0) < 0 ) + // continue; + printk(BIOS_DEBUG, "smbus: %02x", device); + for(j = 0; j < 256; j++) { + int status; + u8 byte; + status = spd_read_byte(device, j); + if (status < 0) { + break; + } + if ((j & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%02x: ",j); + } + byte = status & 0xff; + printk(BIOS_DEBUG, "%02x ", byte); + } + printk(BIOS_DEBUG, "\n"); + } +} + +static void enable_mainboard_devices(void) +{ + u32 dev; + + pci_conf1_find_device(0x1106, 0x3227, &dev); + /* Disable GP3 */ + pci_conf1_write_config8(dev, 0x98, 0x00); + + pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata + pci_conf1_write_config8(dev, 0x51, 0x1f); + pci_conf1_write_config8(dev, 0x58, 0x60); + pci_conf1_write_config8(dev, 0x59, 0x80); + pci_conf1_write_config8(dev, 0x5b, 0x08); + + pci_conf1_find_device(0x1106, 0x0571, &dev); + + /* Make it respond to IO space */ + pci_conf1_write_config8(dev, 0x04, 0x07); + + /* Compatibility mode addresses */ + //pci_conf1_write_config32(dev, 0x10, 0); + //pci_conf1_write_config32(dev, 0x14, 0); + //pci_conf1_write_config32(dev, 0x18, 0); + //pci_conf1_write_config32(dev, 0x1b, 0); + + /* Native mode base address */ + //pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1); + + pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3 + pci_conf1_write_config8(dev, 0x41, 0xf2); + pci_conf1_write_config8(dev, 0x42, 0x09); + /* I'll be damned if I know what these do */ + pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e + pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00 +} + +static void enable_shadow_ram(void) +{ + u8 shadowreg; + + printk(BIOS_DEBUG, "Enabling shadow ram\n"); + /* Enable shadow ram as normal dram */ + /* 0xc0000-0xcffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); + /* 0xd0000-0xdffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); + /* 0xe0000-0xeffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); + + /* 0xf0000-0xfffff */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); + + /* Do it again for the vlink controller */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); +} + +static void enable_vlink(void) +{ + printk(BIOS_DEBUG, "Enabling Via V-Link\n"); + + /* Enable V-Link statically in 8x mode, using Jetway default values */ +//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01 + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); + //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); +//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00 + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); + + /* This has to be done last, I think */ + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); +} + +int main(void) +{ + struct board_info ctrl[] = { + { + .d0f2 = PCI_BDF(0, 0, 2), + .d0f3 = PCI_BDF(0, 0, 3), + .d0f4 = PCI_BDF(0, 0, 4), + .d0f7 = PCI_BDF(0, 0, 7), + .d1f0 = PCI_BDF(0, 1, 0), + .spd_channel0 = {0x50}, + }, + }; + + printk(BIOS_DEBUG, "In initram.c main()\n"); + + enable_vlink(); + enable_mainboard_devices(); + enable_shadow_ram(); + + c7_cpu_setup(PCI_BDF(0, 0, 2)); + + enable_smbus(SMBUS_IO_BASE); + //find_smbus_devices(0x00, 0xff); + sdram_set_registers(ctrl); + sdram_set_spd_registers(ctrl); + ddr2_sdram_enable(ctrl); + + //ram_check(0, 640*1024); + //ram_check((8 * 1024 * 1024), (16 * 1024 * 1024)); + + return 0; +} +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <io.h> +#include <spd.h> +#include <via_c7.h> +#include <arch/x86/pci_ops.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <superio/fintek/f71805f/f71805f.h> +#include <southbridge/via/vt8237/vt8237.h> +#include <northbridge/via/cn700/cn700.h> + +#define SMBUS_IO_BASE 0x0400 + +u8 spd_read_byte(u16 dev, u8 addr) +{ + return smbus_read_byte(dev, addr, SMBUS_IO_BASE); +} + +void find_smbus_devices(u8 min, u8 max) +{ + u8 dev; + u8 result; + for(dev = min; dev < max; dev++) + { + result = spd_read_byte(dev, SPD_MEMORY_TYPE); + switch(result) + { + case SPD_MEMORY_TYPE_SDRAM: printk(BIOS_DEBUG, + "Possible SDRAM spd at address 0x%2x\n", dev); + break; + case SPD_MEMORY_TYPE_SDRAM_DDR: printk(BIOS_DEBUG, + "Possible DDR SDRAM spd at address 0x%2x\n", dev); + break; + case SPD_MEMORY_TYPE_SDRAM_DDR2: printk(BIOS_DEBUG, + "Possible DDR2 SDRAM spd at address 0x%2x\n", dev); + break; + }; + } +} + + +void dump_smbus_registers(void) +{ + int device; + for(device = 1; device < (int)0x80; device++) { + int j; + //if(spd_read_byte(device, 0) < 0 ) + // continue; + printk(BIOS_DEBUG, "smbus: %02x", device); + for(j = 0; j < 256; j++) { + int status; + u8 byte; + status = spd_read_byte(device, j); + if (status < 0) { + break; + } + if ((j & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%02x: ",j); + } + byte = status & 0xff; + printk(BIOS_DEBUG, "%02x ", byte); + } + printk(BIOS_DEBUG, "\n"); + } +} + +static void enable_mainboard_devices(void) +{ + u32 dev; + + pci_conf1_find_device(0x1106, 0x3227, &dev); + /* Disable GP3 */ + pci_conf1_write_config8(dev, 0x98, 0x00); + + pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata + pci_conf1_write_config8(dev, 0x51, 0x1f); + pci_conf1_write_config8(dev, 0x58, 0x60); + pci_conf1_write_config8(dev, 0x59, 0x80); + pci_conf1_write_config8(dev, 0x5b, 0x08); + + pci_conf1_find_device(0x1106, 0x0571, &dev); + + /* Make it respond to IO space */ + pci_conf1_write_config8(dev, 0x04, 0x07); + + /* Compatibility mode addresses */ + //pci_conf1_write_config32(dev, 0x10, 0); + //pci_conf1_write_config32(dev, 0x14, 0); + //pci_conf1_write_config32(dev, 0x18, 0); + //pci_conf1_write_config32(dev, 0x1b, 0); + + /* Native mode base address */ + //pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1); + + pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3 + pci_conf1_write_config8(dev, 0x41, 0xf2); + pci_conf1_write_config8(dev, 0x42, 0x09); + /* I'll be damned if I know what these do */ + pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e + pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00 +} + +static void enable_shadow_ram(void) +{ + u8 shadowreg; + + printk(BIOS_DEBUG, "Enabling shadow ram\n"); + /* Enable shadow ram as normal dram */ + /* 0xc0000-0xcffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); + /* 0xd0000-0xdffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); + /* 0xe0000-0xeffff */ + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); + + /* 0xf0000-0xfffff */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); + + /* Do it again for the vlink controller */ + shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); + shadowreg |= 0x30; + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); +} + +static void enable_vlink(void) +{ + printk(BIOS_DEBUG, "Enabling Via V-Link\n"); + + /* Enable V-Link statically in 8x mode, using Jetway default values */ +//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01 + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); + //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); +//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00 + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); + + /* This has to be done last, I think */ + pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); +} + +int main(void) +{ + struct board_info ctrl[] = { + { + .d0f2 = PCI_BDF(0, 0, 2), + .d0f3 = PCI_BDF(0, 0, 3), + .d0f4 = PCI_BDF(0, 0, 4), + .d0f7 = PCI_BDF(0, 0, 7), + .d1f0 = PCI_BDF(0, 1, 0), + .spd_channel0 = {0x50}, + }, + }; + + printk(BIOS_DEBUG, "In initram.c main()\n"); + + enable_vlink(); + enable_mainboard_devices(); + enable_shadow_ram(); + + c7_cpu_setup(PCI_BDF(0, 0, 2)); + + enable_smbus(SMBUS_IO_BASE); + //find_smbus_devices(0x00, 0xff); + sdram_set_registers(ctrl); + sdram_set_spd_registers(ctrl); + ddr2_sdram_enable(ctrl); + + //ram_check(0, 640*1024); + //ram_check((8 * 1024 * 1024), (16 * 1024 * 1024)); + + return 0; +} Added: coreboot-v3/mainboard/jetway/j7f2/mainboard.c =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/mainboard.c (rev 0) +++ coreboot-v3/mainboard/jetway/j7f2/mainboard.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <mainboard.h> +#include <config.h> +#include <types.h> +#include <lib.h> +#include <console.h> +#include <cpu.h> +#include <globalvars.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> + +/* Nothing to do (yet) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <mainboard.h> +#include <config.h> +#include <types.h> +#include <lib.h> +#include <console.h> +#include <cpu.h> +#include <globalvars.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> + +/* Nothing to do (yet) */ Added: coreboot-v3/mainboard/jetway/j7f2/mainboard.h =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/mainboard.h (rev 0) +++ coreboot-v3/mainboard/jetway/j7f2/mainboard.h 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CPU_ADDR_BITS 40 + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CPU_ADDR_BITS 40 + Added: coreboot-v3/mainboard/jetway/j7f2/stage1.c =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/stage1.c (rev 0) +++ coreboot-v3/mainboard/jetway/j7f2/stage1.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <io.h> +#include <arch/x86/pci_ops.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <superio/fintek/f71805f/f71805f.h> +#include <northbridge/via/cn700/cn700.h> + +/* Placeholders, build fails without them */ +void stop_ap(void) +{ + //int noop; +} + +void hardware_stage1(void) +{ + u32 dev; + + post_code(POST_START_OF_MAIN); + f71805f_enable_serial(0x2e); + + /* Enable multifunction for northbridge. */ + pci_conf1_write_config8(0x00, 0x4f, 0x01); + + printk(BIOS_SPEW, "In hardware_stage1()\n"); + /* Disabled GP3, to keep the system from rebooting automatically */ + //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev); + dev = PCI_BDF(0, 17, 0); + pci_conf1_write_config8(dev, 0x98, 0x00); +} + +void mainboard_pre_payload(void) +{ + //banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <io.h> +#include <arch/x86/pci_ops.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <superio/fintek/f71805f/f71805f.h> +#include <northbridge/via/cn700/cn700.h> + +/* Placeholders, build fails without them */ +void stop_ap(void) +{ + //int noop; +} + +void hardware_stage1(void) +{ + u32 dev; + + post_code(POST_START_OF_MAIN); + f71805f_enable_serial(0x2e); + + /* Enable multifunction for northbridge. */ + pci_conf1_write_config8(0x00, 0x4f, 0x01); + + printk(BIOS_SPEW, "In hardware_stage1()\n"); + /* Disabled GP3, to keep the system from rebooting automatically */ + //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev); + dev = PCI_BDF(0, 17, 0); + pci_conf1_write_config8(dev, 0x98, 0x00); +} + +void mainboard_pre_payload(void) +{ + //banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} Modified: coreboot-v3/northbridge/via/cn700/Makefile =================================================================== --- coreboot-v3/northbridge/via/cn700/Makefile 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/northbridge/via/cn700/Makefile 2008-10-31 18:13:20 UTC (rev 967) @@ -20,6 +20,9 @@ ifeq ($(CONFIG_NORTHBRIDGE_VIA_CN700),y) -STAGE2_CHIPSET_SRC += +STAGE2_CHIPSET_SRC += $(src)/northbridge/via/cn700/stage2.c \ + $(src)/northbridge/via/cn700/agp.c \ + $(src)/northbridge/via/cn700/pci.c \ + $(src)/northbridge/via/cn700/vga.c endif Added: coreboot-v3/northbridge/via/cn700/agp.c =================================================================== --- coreboot-v3/northbridge/via/cn700/agp.c (rev 0) +++ coreboot-v3/northbridge/via/cn700/agp.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console.h> +#include <io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "cn700.h" + +/* This is the main AGP device, and only one used when configured for AGP 2.0 */ +static void agp_init(struct device *dev) +{ + u32 reg32; + + /* Some of this may not be necessary (should be handled by the OS). */ + printk(BIOS_DEBUG, "Enabling AGP.\n"); + + /* Allow R/W access to AGP registers. */ + pci_write_config8(dev, 0x4d, 0x15); + + /* Setup PCI latency timer. */ + pci_write_config8(dev, 0xd, 0x8); + + /* + * Set to AGP 3.0 Mode, which should theoretically render the rest of + * the registers set here pointless. + */ + pci_write_config8(dev, 0x84, 0xb); + + /* AGP Request Queue Size */ + pci_write_config8(dev, 0x4a, 0x1f); + + /* + * AGP Hardware Support (default 0xc4) + * 7: AGP SBA Enable (1 to Enable) + * 6: AGP Enable + * 5: Reserved + * 4: Fast Write Enable + * 3: AGP8X Mode Enable + * 2: AGP4X Mode Enable + * 1: AGP2X Mode Enable + * 0: AGP1X Mode Enable + */ + pci_write_config8(dev, 0x4b, 0xc4); + + /* Enable AGP Backdoor */ + pci_write_config8(dev, 0xb5, 0x03); + + /* Set aperture to 32 MB. */ + /* TODO: Use config option, explain how it works. */ + pci_write_config32(dev, 0x94, 0x00010f38); + /* Set GART Table Base Address (31:12). */ + pci_write_config32(dev, 0x98, (0x1558 << 12)); + /* Set AGP Aperture Base. */ + pci_write_config32(dev, 0x10, 0xf8000008); + + /* Enable CPU/PMSTR GART Access. */ + reg32 = pci_read_config8(dev, 0xbf); + reg32 |= 0x80; + pci_write_config8(dev, 0xbf, reg32); + + /* Enable AGP Aperture. */ + reg32 = pci_read_config32(dev, 0x94); + reg32 |= (3 << 7); + pci_write_config32(dev, 0x90, reg32); + + /* AGP Control */ + pci_write_config8(dev, 0xbc, 0x21); + pci_write_config8(dev, 0xbd, 0xd2); + + /* + * AGP Pad, driving strength, and delay control. All this should be + * constant, seeing as the VGA controller is onboard. + */ + pci_write_config8(dev, 0x40, 0xc7); + pci_write_config8(dev, 0x41, 0xdb); + pci_write_config8(dev, 0x42, 0x10); + pci_write_config8(dev, 0x43, 0xdb); + pci_write_config8(dev, 0x44, 0x24); + + /* AGPC CKG Control */ + pci_write_config8(dev, 0xc0, 0x02); + pci_write_config8(dev, 0xc1, 0x02); +} + +struct device_operations cn700_agp = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_CN700_AGP}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + //.phase4_set_resources = pci_dev_set_resources, + //.phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = agp_init, +}; Modified: coreboot-v3/northbridge/via/cn700/cn700.h =================================================================== --- coreboot-v3/northbridge/via/cn700/cn700.h 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/northbridge/via/cn700/cn700.h 2008-10-31 18:13:20 UTC (rev 967) @@ -18,8 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_VIA_CN700_CN700_H +#define NORTHBRIDGE_VIA_CN700_CN700_H + #include <types.h> - + struct board_info { u32 d0f2, d0f3, d0f4, d0f7, d1f0; u16 spd_channel0[2]; @@ -59,3 +62,5 @@ #define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 + +#endif Added: coreboot-v3/northbridge/via/cn700/memctrl.c =================================================================== --- coreboot-v3/northbridge/via/cn700/memctrl.c (rev 0) +++ coreboot-v3/northbridge/via/cn700/memctrl.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "cn700.h" + +static void memctrl_init(struct device *dev) +{ + struct device *vlink_dev; + u16 reg16; + u8 ranks, pagec, paged, pagee, pagef, shadowreg; + + /* Set up the VGA framebuffer size. */ + reg16 = (log2(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15); + pci_write_config16(dev, 0xa0, reg16); + + /* Set up VGA timers. */ + pci_write_config8(dev, 0xa2, 0x44); + + for (ranks = 0x4b; ranks >= 0x48; ranks--) { + if (pci_read_config8(dev, ranks)) { + ranks -= 0x48; + break; + } + } + if (ranks == 0x47) + ranks = 0x00; + reg16 = 0xaae0; + reg16 |= ranks; + /* GMINT Misc. FrameBuffer rank */ + pci_write_config16(dev, 0xb0, reg16); + /* AGPCINT Misc. */ + pci_write_config8(dev, 0xb8, 0x08); + + /* TODO: This doesn't belong here. At the very least make it a dts + * option */ + + /* Shadow RAM */ + pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30; + /* PAGE C, D, E are all read write enable */ + pci_write_config8(dev, 0x80, pagec); + pci_write_config8(dev, 0x81, paged); + pci_write_config8(dev, 0x82, pagee); + /* PAGE F are read/writable */ + shadowreg = pci_read_config8(dev, 0x83); + shadowreg |= pagef; + pci_write_config8(dev, 0x83, shadowreg); + /* vlink mirror */ + vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_CN700_VLINK, 0); + if (vlink_dev) { + pci_write_config8(vlink_dev, 0x61, pagec); + pci_write_config8(vlink_dev, 0x62, paged); + pci_write_config8(vlink_dev, 0x64, pagee); + + shadowreg = pci_read_config8(vlink_dev, 0x63); + shadowreg |= pagef; + pci_write_config8(vlink_dev, 0x63, shadowreg); + } +} + +static const struct device_operations memctrl_operations = { + .read_resources = cn700_noop, + .init = memctrl_init, +}; + +static const struct pci_driver memctrl_driver __pci_driver = { + .ops = &memctrl_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, +}; Added: coreboot-v3/northbridge/via/cn700/pci.c =================================================================== --- coreboot-v3/northbridge/via/cn700/pci.c (rev 0) +++ coreboot-v3/northbridge/via/cn700/pci.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,61 @@ +#include <types.h> +#include <console.h> +#include <io.h> +#include <lib.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/x86/cpu.h> +#include <statictree.h> +#include <config.h> +#include "cn700.h" + +/* + * This is the AGP 3.0 and PCI bridge @B0 Device 1 Func 0. When using AGP 3.0, the + * config in this device takes presidence. We configure both just to be safe. + */ +static void pci_bridge_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Setting up AGP bridge device\n"); + + pci_write_config16(dev, 0x4, 0x0007); + + /* Secondary Bus Number */ + pci_write_config8(dev, 0x19, 0x01); + /* Subordinate Bus Number */ + pci_write_config8(dev, 0x1a, 0x01); + /* I/O Base */ + pci_write_config8(dev, 0x1c, 0xd0); + /* I/O Limit */ + pci_write_config8(dev, 0x1d, 0xd0); + + /* Memory Base */ + pci_write_config16(dev, 0x20, 0xfb00); + /* Memory Limit */ + pci_write_config16(dev, 0x22, 0xfcf0); + /* Prefetchable Memory Base */ + pci_write_config16(dev, 0x24, 0xf400); + /* Prefetchable Memory Limit */ + pci_write_config16(dev, 0x26, 0xf7f0); + /* Enable VGA Compatible Memory/IO Range */ + pci_write_config8(dev, 0x3e, 0x08); + + /* Second PCI Bus Control (see datasheet) */ + pci_write_config8(dev, 0x40, 0x83); + pci_write_config8(dev, 0x41, 0x43); + pci_write_config8(dev, 0x42, 0xe2); + pci_write_config8(dev, 0x43, 0x44); + pci_write_config8(dev, 0x44, 0x34); + pci_write_config8(dev, 0x45, 0x72); +} + +struct device_operations cn700_pci_bridge = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_CN700_BRIDGE}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_dev_read_resources, + //.phase4_set_resources = pci_dev_set_resources, + //.phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = pci_bridge_init, +}; Added: coreboot-v3/northbridge/via/cn700/stage2.c =================================================================== --- coreboot-v3/northbridge/via/cn700/stage2.c (rev 0) +++ coreboot-v3/northbridge/via/cn700/stage2.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console.h> +#include <io.h> +#include <lib.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/x86/cpu.h> +#include <statictree.h> +#include <config.h> + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + + best = *best_p; + if (!best || (best->base > new->base)) + best = new; + *best_p = best; +} + +static u32 find_pci_tolm(struct bus *bus) +{ + struct resource *min; + u32 tolm; + + printk(BIOS_DEBUG, "Entering find_pci_tolm\n"); + + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, + tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) + tolm = min->base; + + printk(BIOS_DEBUG, "Leaving find_pci_tolm\n"); + + return tolm; +} + +static const u8 ramregs[4] = {0x43, 0x42, 0x41, 0x40}; + +static void pci_domain_set_resources(struct device *dev) +{ + struct device *mc_dev; + u32 pci_tolm; + + printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); + + pci_tolm = find_pci_tolm(&dev->link[0]); + mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0); + + if (mc_dev) { + u32 tomk, tolmk; + u8 rambits; + int i, idx; + + /* + * Once the register value is not zero, the RAM size is + * this register's value multiply 64 * 1024 * 1024. + */ + for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { + rambits = pci_read_config8(mc_dev, ramregs[i]); + if (rambits != 0) + break; + } + + tomk = rambits * 64 * 1024; + printk(BIOS_SPEW, "tomk is 0x%x\n", tomk); + /* Compute the Top Of Low Memory (TOLM), in Kb. */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does does not overlap the memory. */ + tolmk = tomk; + } + /* Report the memory regions. */ + idx = 10; + /* TODO: Hole needed? */ + ram_resource(dev, idx++, 0, 640); /* First 640k */ + /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ + ram_resource(dev, idx++, 768, + (tolmk - 768 - CONFIG_CN700_VIDEO_MB_32 * 1024)); + } + phase4_assign_resources(&dev->link[0]); +} + +static void cpu_bus_init(struct device *dev) +{ +#warning "cpu_bus_init() empty, what should it do?" + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); + printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__); +} + +static void cpu_bus_noop(struct device *dev) +{ +} + +/** Operations for when the northbridge is running a PCI domain. */ +struct device_operations cn700_north_domain = { + .id = {.type = DEVICE_ID_PCI_DOMAIN, + {.pci_domain = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_CN700_AGP}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_domain_scan_bus, + .phase4_read_resources = pci_domain_read_resources, + .phase4_set_resources = pci_domain_set_resources, + .phase5_enable_resources = enable_childrens_resources, + .phase6_init = 0, +}; + +/** Operations for when the northbridge is running an APIC cluster. */ +struct device_operations cn700_north_apic = { + .id = {.type = DEVICE_ID_APIC_CLUSTER, + {.apic_cluster = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_CN700_AGP}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = cpu_bus_noop, + .phase4_set_resources = cpu_bus_noop, + .phase5_enable_resources = cpu_bus_noop, + .phase6_init = cpu_bus_init, +}; Added: coreboot-v3/northbridge/via/cn700/stage2.h =================================================================== --- coreboot-v3/northbridge/via/cn700/stage2.h (rev 0) +++ coreboot-v3/northbridge/via/cn700/stage2.h 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_VIA_CN700_STAGE2_H +#define NORTHBRIDGE_VIA_CN700_STAGE2_H + +extern unsigned int cn700_scan_root_bus(device_t root, unsigned int max); + +#endif Added: coreboot-v3/northbridge/via/cn700/vga.c =================================================================== --- coreboot-v3/northbridge/via/cn700/vga.c (rev 0) +++ coreboot-v3/northbridge/via/cn700/vga.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console.h> +#include <io.h> +#include <types.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "cn700.h" + +void write_protect_vgabios(void) +{ + /* Don't bother for now. */ +#warning "CN700 VGA BIOS write protect needs to be completed" +} + +static void vga_init(struct device *dev) +{ + u8 reg8; + + printk(BIOS_DEBUG, "Initializing VGA\n"); + + /* Set memory rate to 200 MHz. */ + outb(0x3d, CRTM_INDEX); + reg8 = inb(CRTM_DATA); + reg8 &= 0x0f; + reg8 |= (0x1 << 4); + outb(0x3d, CRTM_INDEX); + outb(reg8, CRTM_DATA); + + /* Set framebuffer size. */ + reg8 = (CONFIG_CN700_VIDEO_MB_32 / 4); + outb(0x39, SR_INDEX); + outb(reg8, SR_DATA); + + pci_write_config8(dev, 0x04, 0x07); + pci_write_config8(dev, 0x0d, 0x20); + /* TODO: IIRC these need to be fixed for different VGA memory sizes */ + pci_write_config32(dev, 0x10, 0xf4000008); + pci_write_config32(dev, 0x14, 0xfb000000); +} + +static void vga_read_resources(struct device *dev) +{ + dev->rom_address = (0xffffffff - (u32)(1024 * CONFIG_COREBOOT_ROMSIZE_KB - 1)); + dev->on_mainboard = 1; + pci_dev_read_resources(dev); +} + +struct device_operations cn700_vga = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_CN700_VGA}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_read_resources = vga_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = vga_init, +}; Modified: coreboot-v3/southbridge/via/vt8237/Makefile =================================================================== --- coreboot-v3/southbridge/via/vt8237/Makefile 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/southbridge/via/vt8237/Makefile 2008-10-31 18:13:20 UTC (rev 967) @@ -20,6 +20,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237),y) -STAGE2_CHIPSET_SRC += +STAGE2_CHIPSET_SRC += $(src)/southbridge/via/vt8237/vt8237.c \ + $(src)/southbridge/via/vt8237/lpc.c \ + $(src)/southbridge/via/vt8237/ide.c \ + $(src)/southbridge/via/vt8237/sata.c endif Added: coreboot-v3/southbridge/via/vt8237/ide.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/ide.c (rev 0) +++ coreboot-v3/southbridge/via/vt8237/ide.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Based on other VIA SB code. */ +#include <types.h> +#include <console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include "vt8237.h" + +/** + * No native mode. Interrupts from unconnected HDDs might occur if + * IRQ14/15 is used for PCI. Therefore no native mode support. + */ +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8237_ide_config *sb = + (struct southbridge_via_vt8237_ide_config *)dev->device_configuration; + + u8 enables; + u32 cablesel; + + printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", + sb->ide0_enable ? "enabled" : "disabled"); + printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", + sb->ide1_enable ? "enabled" : "disabled"); + enables = pci_read_config8(dev, IDE_CS) & ~0x3; + enables |= (sb->ide0_enable << 1) | sb->ide1_enable; + pci_write_config8(dev, IDE_CS, enables); + enables = pci_read_config8(dev, IDE_CS); + printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); + + /* Enable only compatibility mode. */ + enables = pci_read_config8(dev, IDE_CONF_II); + enables &= ~0xc0; + pci_write_config8(dev, IDE_CONF_II, enables); + enables = pci_read_config8(dev, IDE_CONF_II); + printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); + + /* Enable prefetch buffers. */ + enables = pci_read_config8(dev, IDE_CONF_I); + enables |= 0xf0; + pci_write_config8(dev, IDE_CONF_I, enables); + + /* Flush FIFOs at half. */ + enables = pci_read_config8(dev, IDE_CONF_FIFO); + enables &= 0xf0; + enables |= (1 << 2) | (1 << 0); + pci_write_config8(dev, IDE_CONF_FIFO, enables); + + /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ + enables = pci_read_config8(dev, IDE_MISC_I); + enables &= 0xe2; + enables |= (1 << 4) | (1 << 3); + pci_write_config8(dev, IDE_MISC_I, enables); + + /* Use memory read multiple, Memory-Write-and-Invalidate. */ + enables = pci_read_config8(dev, IDE_MISC_II); + enables |= (1 << 2) | (1 << 3); + pci_write_config8(dev, IDE_MISC_II, enables); + + /* Force interrupts to use compat mode. */ + pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + /* Cable guy... */ + cablesel = pci_read_config32(dev, IDE_UDMA); + cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4)); + cablesel |= (sb->ide0_80pin_cable << 28) | + (sb->ide0_80pin_cable << 20) | + (sb->ide1_80pin_cable << 12) | + (sb->ide1_80pin_cable << 4); + pci_write_config32(dev, IDE_UDMA, cablesel); +} + +struct device_operations vt8237_ide = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237_PATA}}}, + .constructor = default_device_constructor, + .phase2_fixup = vt8237_enable, + .phase3_scan = 0, + //.phase4_enable_disable = vt8237_enable, + //.phase4_read_resources = pci_dev_read_resources, + //.phase4_set_resources = pci_dev_set_resources, + //.phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = ide_init, +}; Added: coreboot-v3/southbridge/via/vt8237/ide.dts =================================================================== --- coreboot-v3/southbridge/via/vt8237/ide.dts (rev 0) +++ coreboot-v3/southbridge/via/vt8237/ide.dts 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "vt8237_ide"; + ide0_enable = "1"; + ide1_enable = "1"; + ide0_80pin_cable = "0"; + ide1_80pin_cable = "0"; +}; Added: coreboot-v3/southbridge/via/vt8237/lpc.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/lpc.c (rev 0) +++ coreboot-v3/southbridge/via/vt8237/lpc.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,470 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Inspiration from other VIA SB code. */ + +#include <types.h> +#include <io.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/x86/lapic.h> +#include <mc146818rtc.h> +#include <keyboard.h> +#include <legacy.h> +#include <statictree.h> +#include <config.h> +#include "vt8237.h" + +#define ALL (0xff << 24) +#define NONE (0) +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + +static struct ioapicreg { + u32 reg; + u32 value_low; + u32 value_high; +} ioapic_table[] = { + /* IO-APIC virtual wire mode configuration. */ + /* mask, trigger, polarity, destination, delivery, vector */ + {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | + ExtINT, NONE}, + {1, DISABLED, NONE}, + {2, DISABLED, NONE}, + {3, DISABLED, NONE}, + {4, DISABLED, NONE}, + {5, DISABLED, NONE}, + {6, DISABLED, NONE}, + {7, DISABLED, NONE}, + {8, DISABLED, NONE}, + {9, DISABLED, NONE}, + {10, DISABLED, NONE}, + {11, DISABLED, NONE}, + {12, DISABLED, NONE}, + {13, DISABLED, NONE}, + {14, DISABLED, NONE}, + {15, DISABLED, NONE}, + {16, DISABLED, NONE}, + {17, DISABLED, NONE}, + {18, DISABLED, NONE}, + {19, DISABLED, NONE}, + {20, DISABLED, NONE}, + {21, DISABLED, NONE}, + {22, DISABLED, NONE}, + {23, DISABLED, NONE}, +}; + +static void setup_ioapic(struct device *dev) +{ + struct southbridge_via_vt8237_lpc_config *sb = + (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration; + + u32 value_low, value_high, val; + volatile u32 *l; + int i; + + /* All delivered to CPU0. */ + ioapic_table[0].value_high = (lapicid()) << (56 - 32); + l = (void *)sb->apic_base; + + /* Set APIC to FSB message bus. */ + l[0] = 0x3; + val = l[4]; + l[4] = (val & 0xFFFFFE) | 1; + + /* Set APIC ADDR - this will be VT8237_APIC_ID. */ + l[0] = 0; + val = l[4]; + l[4] = (val & 0xF0FFFF) | (sb->apic_id << 24); + + for (i = 0; i < ARRAY_SIZE(ioapic_table); i++) { + l[0] = (ioapic_table[i].reg * 2) + 0x10; + l[4] = ioapic_table[i].value_low; + value_low = l[4]; + l[0] = (ioapic_table[i].reg * 2) + 0x11; + l[4] = ioapic_table[i].value_high; + value_high = l[4]; + + if ((i == 0) && (value_low == 0xffffffff)) { + printk(BIOS_WARNING, "IO APIC not responding.\n"); + return; + } + } +} + +/** Set up PCI IRQ routing, route everything through APIC. */ +static void pci_routing_fixup(struct device *dev) +{ + /* PCI PNP Interrupt Routing INTE/F - disable */ + pci_write_config8(dev, 0x44, 0x00); + + /* PCI PNP Interrupt Routing INTG/H - disable */ + pci_write_config8(dev, 0x45, 0x00); + + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + + /* PCI Interrupt Polarity */ + pci_write_config8(dev, 0x54, 0x00); + + /* PCI INTA# Routing */ + pci_write_config8(dev, 0x55, 0x00); + + /* PCI INTB#/C# Routing */ + pci_write_config8(dev, 0x56, 0x00); + + /* PCI INTD# Routing */ + pci_write_config8(dev, 0x57, 0x00); +} + +/** + * Set up the power management capabilities directly into ACPI mode. + * This avoids having to handle any System Management Interrupts (SMIs). + */ +static void setup_pm(struct device *dev) +{ + struct southbridge_via_vt8237_lpc_config *sb = + (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration; + + /* Debounce LID and PWRBTN# Inputs for 16ms. */ + pci_write_config8(dev, 0x80, 0x20); + + /* Set ACPI base address to I/O sb->acpi_io_base. */ + pci_write_config16(dev, 0x88, sb->acpi_io_base | 0x1); + + /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ + pci_write_config8(dev, 0x82, 0x40 | sb->acpi_irq); + + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + pci_write_config16(dev, 0x84, 0x30b2); + + /* SMI output level to low, 7.5us throttle clock */ + pci_write_config8(dev, 0x8d, 0x18); + + /* GP Timer Control 1s */ + pci_write_config8(dev, 0x93, 0x88); + + /* + * 7 = SMBus clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp + * 2 = GPO2 is GPIO + */ + pci_write_config8(dev, 0x94, 0xa4); + + /* + * 7 = stp to sust delay 1msec + * 6 = SUSST# Deasserted Before PWRGD for STD + * 4 = PWRGOOD reset on VT8237A/S + * 3 = GPO26/GPO27 is GPO + * 2 = Disable Alert on Lan + */ + pci_write_config8(dev, 0x95, 0xcc); + + /* Disable GP3 timer. */ + pci_write_config8(dev, 0x98, 0); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* Clear status events. */ + outw(0xffff, sb->acpi_io_base + 0x00); + outw(0xffff, sb->acpi_io_base + 0x20); + outw(0xffff, sb->acpi_io_base + 0x28); + outl(0xffffffff, sb->acpi_io_base + 0x30); + + /* Disable SCI on GPIO. */ + outw(0x0, sb->acpi_io_base + 0x22); + + /* Disable SMI on GPIO. */ + outw(0x0, sb->acpi_io_base + 0x24); + + /* Disable all global enable SMIs. */ + outw(0x0, sb->acpi_io_base + 0x2a); + + /* All SMI off, both IDE buses ON, PSON rising edge. */ + outw(0x0, sb->acpi_io_base + 0x2c); + + /* Primary activity SMI disable. */ + outl(0x0, sb->acpi_io_base + 0x34); + + /* GP timer reload on none. */ + outl(0x0, sb->acpi_io_base + 0x38); + + /* Disable extended IO traps. */ + outb(0x0, sb->acpi_io_base + 0x42); + + /* SCI is generated for RTC/pwrBtn/slpBtn. */ + outw(0x001, sb->acpi_io_base + 0x04); +} + +static void vt8237_common_init(struct device *dev) +{ + u8 enables, byte; + + /* Enable addr/data stepping. */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte |= PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); + + /* Enable the internal I/O decode. */ + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + /* + * ROM decode + * bit range + * 7 000E0000h-000EFFFFh + * 6 FFF00000h-FFF7FFFFh + * 5 FFE80000h-FFEFFFFFh + * 4 FFE00000h-FFE7FFFFh + * 3 FFD80000h-FFDFFFFFh + * 2 FFD00000h-FFD7FFFFh + * 1 FFC80000h-FFCFFFFFh + * 0 FFC00000h-FFC7FFFFh + * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. + */ + pci_write_config8(dev, 0x41, 0x7f); + + /* + * Set bit 6 of 0x40 (I/O recovery time). + * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so + * that PCI interrupts can be properly marked as level triggered. + */ + enables = pci_read_config8(dev, 0x40); + enables |= 0x44; + pci_write_config8(dev, 0x40, enables); + + /* Line buffer control */ + enables = pci_read_config8(dev, 0x42); + enables |= 0xf8; + pci_write_config8(dev, 0x42, enables); + + /* Delay transaction control */ + pci_write_config8(dev, 0x43, 0xb); + + /* I/O recovery time, default IDE routing */ + pci_write_config8(dev, 0x4c, 0x44); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* + * Bit | Meaning + * ------------- + * 3 | Bypass APIC De-Assert Message (1=Enable) + * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" + * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch + * 0 | Dynamic Clock Gating Main Switch (1=Enable) + */ + pci_write_config8(dev, 0x5b, 0xb); + + /* Set 0x58 to 0x43 APIC and RTC. */ + pci_write_config8(dev, 0x58, 0x43); + + /* Enable serial IRQ, 6PCI clocks. */ + pci_write_config8(dev, 0x52, 0x9); + + /* Power management setup */ + setup_pm(dev); + + /* Enable the RTC. */ + enables = pci_read_config8(dev, 0x51); + enables |= (1 << 3); + pci_write_config8(dev, 0x51, enables); + + /* Start the RTC. */ + rtc_init(0); +} + +static void vt8237_read_resources(struct device *dev) +{ + struct southbridge_via_vt8237_lpc_config *sb = + (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration; + + struct resource *res; + + pci_dev_read_resources(dev); + /* Fixed APIC resource */ + res = new_resource(dev, 0x44); + /* Possible breakage */ + res->base = sb->apic_base; + res->size = 256; + res->limit = res->base + res->size - 1; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +/** + * The VT8237 is not a PCI bridge and has no resources of its own (other + * than standard PC I/O addresses), however it does control the ISA bus + * and so we need to manually call enable childrens resources on that bus. + */ +static void vt8237_enable_resources(struct device *dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static void init_keyboard(struct device *dev) +{ + struct southbridge_via_vt8237_lpc_config *sb = + (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration; + + u8 regval; + + if (sb->enable_keyboard) + { + /* Enable PS/2 mouse, Keyboard, and KBC Config */ + regval = pci_read_config8(dev, 0x51); + regval |= (1 << 2)|(1 << 1)|1; + pci_write_config8(dev, 0x51, regval); + + init_pc_keyboard(0x60, 0x64, 0); + } +} + +static void southbridge_init_common(struct device *dev) +{ + vt8237_common_init(dev); + pci_routing_fixup(dev); + setup_ioapic(dev); + setup_i8259(); + init_keyboard(dev); +} + +static void vt8237r_init(struct device *dev) +{ + struct southbridge_via_vt8237_lpc_config *sb = + (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration; + + u8 enables; + + /* + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x9); + + /* REQ5 as PCI request input - should be together with INTE-INTH. */ + pci_write_config8(dev, 0xe4, 0x4); + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + /* + * Set Read Pass Write Control Enable + * (force A2 from APIC FSB to low). + */ + pci_write_config8(dev, 0x48, 0x8c); + + southbridge_init_common(dev); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, sb->acpi_io_base + 0x11); +} + +static void vt8237s_init(struct device *dev) +{ + struct southbridge_via_vt8237_lpc_config *sb = + (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration; + + u32 tmp; + + /* Put SPI base VT8237S_SPI_MEM_BASE. */ + tmp = pci_read_config32(dev, 0xbc); + pci_write_config32(dev, 0xbc, (sb->spi_mem_base >> 8) | (tmp & 0xFF000000)); + + /* Enable SATA LED, VR timer = 100us, VR timer should be fixed. */ + pci_write_config8(dev, 0xe5, 0x69); + + /* + * REQ5 as PCI request input - should be together with INTE-INTH. + * Fast VR timer disable - need for LDTSTOP_L signal. + */ + pci_write_config8(dev, 0xe4, 0xa5); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + /* Host Bus Power Management Control, maybe not needed */ + pci_write_config8(dev, 0x8c, 0x5); + + /* Enable HPET at hpet_addr (from dts), does not work correctly on R. */ + pci_write_config32(dev, 0x68, (sb->hpet_addr | 0x80)); + + southbridge_init_common(dev); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2. + */ + + outb(0xff, sb->acpi_io_base + 0x50); +} + +struct device_operations vt8237r_lpc = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}}, + .constructor = default_device_constructor, + .phase2_fixup = vt8237_enable, + .phase3_scan = scan_static_bus, + .phase4_read_resources = vt8237_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = vt8237_enable_resources, + .phase6_init = vt8237r_init, +}; + +struct device_operations vt8237s_lpc = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237S_LPC}}}, + .constructor = default_device_constructor, + .phase2_fixup = vt8237_enable, + .phase3_scan = scan_static_bus, + .phase4_read_resources = vt8237_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = vt8237_enable_resources, + .phase6_init = vt8237s_init, +}; Added: coreboot-v3/southbridge/via/vt8237/lpc.dts =================================================================== --- coreboot-v3/southbridge/via/vt8237/lpc.dts (rev 0) +++ coreboot-v3/southbridge/via/vt8237/lpc.dts 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "vt8237r_lpc"; + enable_keyboard = "1"; + acpi_io_base = "0x500"; + acpi_irq = "0x9"; + apic_id = "0x2"; + apic_base = "0xfec00000ULL"; + + /* These are unused by vt8237r, but necessary to use + * the same driver for vt8237s */ + spi_mem_base = "0"; + hpet_addr = "0"; +}; + +{ + device_operations = "vt8237s_lpc"; + enable_keyboard = "1"; + acpi_io_base = "0x500"; + acpi_irq = "0x9"; + apic_id = "0x2"; + apic_base = "0xfec00000ULL"; + spi_mem_base = "0xfed02000ULL"; + hpet_addr = "0xfed00000ULL"; +}; Added: coreboot-v3/southbridge/via/vt8237/sata.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/sata.c (rev 0) +++ coreboot-v3/southbridge/via/vt8237/sata.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "vt8237.h" + +/* TODO: use phase2_fixup to disable SATA */ +static void sata_i_init(struct device *dev) +{ + u8 reg; + + printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); + + /* Class IDE Disk */ + reg = pci_read_config8(dev, SATA_MISC_CTRL); + reg &= 0x7f; /* Sub Class Write Protect off */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); + + /* Change the device class to SATA from RAID. */ + pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); + reg |= 0x80; /* Sub Class Write Protect on */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); +} + +/* VT8237R is SATA, VT8237S is SATAII */ +static void sata_ii_init(struct device *dev) +{ + u8 reg; + + sata_i_init(dev); + + /* + * Analog black magic, you may or may not need to adjust 0x60-0x6f, + * depends on PCB. + */ + + /* + * Analog PHY - gen1 + * CDR bandwidth [6:5] = 3 + * Squelch Window Select [4:3] = 1 + * CDR Charge Pump [2:0] = 1 + */ + + /* TODO: Move to DTS */ + + pci_write_config8(dev, 0x64, 0x49); + + /* Adjust driver current source value to 9. */ + reg = pci_read_config8(dev, 0x65); + reg &= 0xf0; + reg |= 0x9; + pci_write_config8(dev, 0x65, reg); + + /* Set all manual termination 50ohm bits [2:0] and enable [4]. */ + reg = pci_read_config8(dev, 0x6a); + reg |= 0xf; + pci_write_config8(dev, 0x6a, reg); + + /* + * Analog PHY - gen2 + * CDR bandwidth [5:4] = 2 + * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e + * CDR Charge Pump [2:0] = 1 + */ + + reg = pci_read_config8(dev, 0x6f); + reg &= 0x08; + reg |= 0x61; + pci_write_config8(dev, 0x6f, reg); + + /* Check if staggered spinup is supported. */ + reg = pci_read_config8(dev, 0x83); + if ((reg & 0x8) == 0) { + /* Start OOB sequence on both drives. */ + reg |= 0x30; + pci_write_config8(dev, 0x83, reg); + } +} + +struct device_operations vt8237r_sata = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_SATA}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + //.phase4_enable_disable = vt8237_enable, + //.phase4_read_resources = pci_dev_read_resources, + //.phase4_set_resources = pci_dev_set_resources, + //.phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = sata_i_init, +}; + +struct device_operations vt8237s_sata = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237S_SATA}}}, + .constructor = default_device_constructor, + .phase2_fixup = 0, + .phase3_scan = 0, + //.phase4_enable_disable = vt8237_enable, + //.phase4_read_resources = pci_dev_read_resources, + //.phase4_set_resources = pci_dev_set_resources, + //.phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = sata_ii_init, +}; Added: coreboot-v3/southbridge/via/vt8237/sata.dts =================================================================== --- coreboot-v3/southbridge/via/vt8237/sata.dts (rev 0) +++ coreboot-v3/southbridge/via/vt8237/sata.dts 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "vt8237r_sata"; + /* configuration variables go here */ +}; + +{ + device_operations = "vt8237s_sata"; +}; Modified: coreboot-v3/southbridge/via/vt8237/stage1.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/stage1.c 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/southbridge/via/vt8237/stage1.c 2008-10-31 18:13:20 UTC (rev 967) @@ -170,14 +170,14 @@ /* 7 = SMBus Clock from RTC 32.768KHz * 5 = Internal PLL reset from susp */ - pci_conf1_write_config8(dev, VT8237R_POWER_WELL, 0xa0); + pci_conf1_write_config8(dev, VT8237_POWER_WELL, 0xa0); /* Enable SMBus. */ - pci_conf1_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, + pci_conf1_write_config16(dev, VT8237_SMBUS_IO_BASE_REG, smbus_io_base | 0x1); /* SMBus Host Configuration, enable. */ - pci_conf1_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); + pci_conf1_write_config8(dev, VT8237_SMBUS_HOST_CONF, 0x01); /* Make it work for I/O. */ pci_conf1_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); Added: coreboot-v3/southbridge/via/vt8237/vt8237.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/vt8237.c (rev 0) +++ coreboot-v3/southbridge/via/vt8237/vt8237.c 2008-10-31 18:13:20 UTC (rev 967) @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "vt8237.h" + +/* + * Datasheet: http://www.via.com.tw/en/downloads/datasheets/chipsets/ + * VT8237R_SouthBridge_Revision2.06_Lead-Free.zip + */ + +void vt8237_enable(struct device *dev) +{ + struct device *lpc_dev; + u16 sb_fn_ctrl; + + const u8 func = dev->path.pci.devfn & 0x7; + const u8 device = dev->path.pci.devfn >> 3; + const int d16_index[6] = {12, 13, 10, 8, 9, 7}; + + + printk(BIOS_DEBUG, "Enabling/Disabling device 0x%x function 0x%x.\n", + device, func); + + if(dev->id.pci.vendor != PCI_VENDOR_ID_VIA) + return; + + lpc_dev = dev_find_slot(0, PCI_BDF(0, 17, 0)); + sb_fn_ctrl = pci_read_config8(lpc_dev, 0x50) << 8; + sb_fn_ctrl |= pci_read_config8(lpc_dev, 0x51); + + if (device == 16) + { + /* If any port is enabled, the first port needs to be enabled */ + if (dev->enabled) + { + sb_fn_ctrl &= ~(1 << d16_index[0]); + sb_fn_ctrl &= ~(1 << d16_index[func]); + } + else + { + sb_fn_ctrl |= (1 << d16_index[func]); + } + } + else if (device == 17) + { + if (func == 5) + { + sb_fn_ctrl &= ~(dev->enabled << 14); + sb_fn_ctrl |= (!dev->enabled << 14); + } + else if (func == 6) + { + sb_fn_ctrl &= ~(dev->enabled << 15); + sb_fn_ctrl |= (!dev->enabled << 15); + } + } + + pci_write_config8(dev, 0x50, (sb_fn_ctrl >> 8) & 0xff); + pci_write_config8(dev, 0x51, sb_fn_ctrl & 0xff); + + /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ +} Modified: coreboot-v3/southbridge/via/vt8237/vt8237.h =================================================================== --- coreboot-v3/southbridge/via/vt8237/vt8237.h 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/southbridge/via/vt8237/vt8237.h 2008-10-31 18:13:20 UTC (rev 967) @@ -22,16 +22,6 @@ #include <types.h> -/* Static resources for the VT8237R southbridge */ - -#define VT8237R_APIC_ID 0x2 -#define VT8237R_ACPI_IO_BASE 0x500 -/* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */ -#define VT8237R_ACPI_IRQ 0x9 -#define VT8237S_SPI_MEM_BASE 0xfed02000ULL -#define VT8237R_HPET_ADDR 0xfed00000ULL -#define VT8237R_APIC_BASE 0xfec00000ULL - /* IDE */ #define IDE_CS 0x40 #define IDE_CONF_I 0x41 @@ -41,10 +31,12 @@ #define IDE_MISC_II 0x45 #define IDE_UDMA 0x50 +#define SATA_MISC_CTRL 0x45 + /* SMBus */ -#define VT8237R_POWER_WELL 0x94 -#define VT8237R_SMBUS_IO_BASE_REG 0xd0 -#define VT8237R_SMBUS_HOST_CONF 0xd2 +#define VT8237_POWER_WELL 0x94 +#define VT8237_SMBUS_IO_BASE_REG 0xd0 +#define VT8237_SMBUS_HOST_CONF 0xd2 #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 @@ -86,5 +78,6 @@ void enable_smbus(u16); u8 smbus_read_byte(u16, u8, u16); +void vt8237_enable(struct device *); #endif Modified: coreboot-v3/superio/fintek/f71805f/superio.c =================================================================== --- coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-31 17:57:42 UTC (rev 966) +++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-31 18:13:20 UTC (rev 967) @@ -97,10 +97,10 @@ static void phase2_setup_scan_bus(struct device *dev); struct device_operations f71805f_ops = { - .phase2_setup_scan_bus = phase2_setup_scan_bus, + .phase3_chip_setup_dev = phase2_setup_scan_bus, + .phase3_enable = f71805f_pnp_enable_resources, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = f71805f_pnp_set_resources, - .phase4_enable_disable = f71805f_pnp_enable_resources, .phase5_enable_resources = f71805f_pnp_enable, .phase6_init = f71805f_init, };
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