Okay, just a short update: I tried moving the mrc.cache file to the end of the cbfs, so it is now on the 4MB chip instead of the 8MB chip:
# ifdtool -f /dev/fd/1 coreboot.rom File coreboot.rom is 12582912 bytes 00000000:00000fff fd 00500000:00bfffff bios 00003000:004fffff me 00001000:00002fff gbe Wrote layout to /dev/fd/1
# cbfstool coreboot.rom print Name Offset Type Size cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 76932 cpu_microcode_blob.bin 0x12d80 microcode 22528 config 0x18600 raw 889 revision 0x189c0 raw 576 cmos.default 0x18c40 cmos_default 256 cmos_layout.bin 0x18d80 cmos_layout 1952 fallback/dsdt.aml 0x19580 raw 13404 payload_config 0x1ca40 raw 1581 payload_revision 0x1d0c0 raw 235 etc/ps2-keyboard-spinup 0x1d200 raw 8 (empty) 0x1d240 null 76952 fallback/ramstage 0x2ff00 stage 89707 pci8086,0166.rom 0x45dc0 optionrom 65536 img/coreinfo 0x55e40 payload 101144 img/nvramcui 0x6e980 payload 108220 fallback/payload 0x89080 payload 62989 img/tint 0x98700 payload 61192 img/memtest 0xa7640 payload 180268 (empty) 0xd36c0 null 3259352 mrc.cache 0x3ef2c0 mrc_cache 65536 bootblock 0x3ff300 bootblock 2984
Now I get this:
Updating MRC cache data. CBFS: 'Master Header Locator' located CBFS at [800100:bfffc0) CBFS: Locating 'mrc.cache' CBFS: Found @ offset 3ef2c0 size 10000 find_current_mrc_cache_local: No valid MRC cache found. flash size 0xc00000 bytes SF: Detected Opaque HW-sequencing with sector size 0x1000, total 0xc00000 Need to erase the MRC cache region of 65536 bytes at fffef400 SF: Erase offset/length not multiple of erase size Finally: write MRC cache update to flash at fffef400 SF: Successfully written 1456 bytes @ 0xbef400 Successfully wrote MRC cache
However, I get the same resume behavior (reboot) as before, and the log still says "No valid MRC cache found". Looks like I need to align the mrc.cache file properly. Going to try that next.
Regards Gert
Hi,
forget everything I said; this was a hardware issue.
When I was first flashing coreboot, I had some problems with my SPI programmer and I was unsure if I had damaged the flash chip. So I replaced it (a MX25L3206E) with another one - a Winbond W25Q32 - that I programmed externally before soldering it on the board. I expected it to be sufficiently similar to the Macronix chip, and when flashing and booting and reprogramming from Linux worked without problems, I did no longer think about it. But obviously there are some subtle differences. I put back the MX25L3206E on the board, and now everyting, including suspend and resume, works fine.
Nevertheless, thanks for your help!
Gert
On Tue, Mar 14, 2017 at 10:40 AM, Gert Menke gert@menke.ac wrote:
Hi,
forget everything I said; this was a hardware issue.
When I was first flashing coreboot, I had some problems with my SPI programmer and I was unsure if I had damaged the flash chip. So I replaced it (a MX25L3206E) with another one - a Winbond W25Q32 - that I programmed externally before soldering it on the board. I expected it to be sufficiently similar to the Macronix chip, and when flashing and booting and reprogramming from Linux worked without problems, I did no longer think about it. But obviously there are some subtle differences. I put back the MX25L3206E on the board, and now everyting, including suspend and resume, works fine.
We would like to have/keep possibility for changing SPI flash parts. It would be nice if someone with knowledge on IFD would take a look if some fields have to be modified and support that in ifdtool. I did found the ID pair 0xEF 0x4016 there in your previous dump, it should have matched your W25Q32.
Kyösti
Nevertheless, thanks for your help!
Gert
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Gert Menke -
Kyösti Mälkki