[LinuxBIOS] Cache As Ram

[Jiangbo W]

Hi,

When using cache as ram how can i ensure that the data in cache can not be
swapped out?

Regards

Jiangbo.W

[yhlu]

what is your CPU?

YH

On 10/26/06, Jiangbo W  wrote:
> Hi,
>
> When using cache as ram how can i ensure that the data in cache can not be
> swapped out?
>
> Regards
> Jiangbo.W
>
> linuxbios mailing list
> [e-mail]
> http://www.openbios.org/mailman/listinfo/linuxbios

[Jiangbo W]

VIA C3, it is compatible with X86, but only have 128K L2 cache. In Intel
Manual Volume 3, i can not find anything about cache as rom

On 10/26/06, yhlu  wrote:
> what is your CPU?
>
> YH
>
> On 10/26/06, Jiangbo W  wrote:
> > Hi,
> >
> > When using cache as ram how can i ensure that the data in cache can not
>
> be
> > swapped out?
> >
> > Regards
> > Jiangbo.W
> >
> > linuxbios mailing list
> > [e-mail]
> > http://www.openbios.org/mailman/listinfo/linuxbios

[Tom Sylla]

Please refer to Chapter 10 "Memory Cache Control" in the Intel manual
you mentioned. Find the Table called "Cache Operating Modes" (Table
10-5 in current version). The way it works is described well in that
table. For CD=1, "Read hits access the cache; read misses do not cause
replacement." and "Write hits update the cache". So that means
anything that is a "hit" acts just like RAM. Nothing too fancy. You
just have to make sure that the area you want to "hit" gets pre-loaded
before you turn the cache back off again.

On 10/26/06, Jiangbo W  wrote:
> VIA C3, it is compatible with X86, but only have 128K L2 cache. In Intel
> Manual Volume 3, i can not find anything about cache as rom
>
> On 10/26/06, yhlu  wrote:
> > what is your CPU?
> >
> > YH
> >
> > On 10/26/06, Jiangbo W <[e-mail] > wrote:
> > > Hi,
> > >
> > > When using cache as ram how can i ensure that the data in cache can not
>
> be
> > > swapped out?
> > >
> > > Regards
> > > Jiangbo.W
> > >
> > > linuxbios mailing list
> > > [e-mail]
> > > http://www.openbios.org/mailman/listinfo/linuxbios

[ron minnich]

On 10/26/06, Tom Sylla  wrote:
> Please refer to Chapter 10 "Memory Cache Control" in the Intel manual
> you mentioned. Find the Table called "Cache Operating Modes" (Table
> 10-5 in current version). The way it works is described well in that
> table. For CD=1, "Read hits access the cache; read misses do not cause
> replacement." and "Write hits update the cache". So that means
> anything that is a "hit" acts just like RAM. Nothing too fancy. You
> just have to make sure that the area you want to "hit" gets pre-loaded
> before you turn the cache back off again.

Thanks  tom!
this is the 'can you read carefully' test that I flunked. It is obvious once
you read it, except I missed it for
5 years :-) Once Eswar pointed it out it was obvious.

ron

[Jiangbo W]

Thanks for all replies!
Ron,  I also flunked :-). I think i should read Intel manual again and
again,

On 10/27/06, ron minnich  wrote:
> On 10/26/06, Tom Sylla  wrote:
> > Please refer to Chapter 10 "Memory Cache Control" in the Intel manual
> > you mentioned. Find the Table called "Cache Operating Modes" (Table
> > 10-5 in current version). The way it works is described well in that
> > table. For CD=1, "Read hits access the cache; read misses do not cause
> > replacement." and "Write hits update the cache". So that means
> > anything that is a "hit" acts just like RAM. Nothing too fancy. You
> > just have to make sure that the area you want to "hit" gets pre-loaded
> > before you turn the cache back off again.
>
> Thanks  tom!
> this is the 'can you read carefully' test that I flunked. It is obvious
> once you read it, except I missed it for
> 5 years :-) Once Eswar pointed it out it was obvious.
>
> ron

[Juergen Beisert]

Hi Jiangbo,

On Thursday 26 October 2006 10:19, Jiangbo W wrote:
> When using cache as ram how can i ensure that the data in cache can not be
> swapped out?

From an old i486 datasheet I got this. And it works on my i486. Maybe it also 
works on other x86 CPUs.

[...]
; Trash all the cache entries, then enable the cache
;
      invd
      mov     eax, cr0
      and     eax, 0x9FFFFFFF
      mov     cr0, eax
;
; Now the cache is enabled, and empty, and not mapped anywhere.  Force
; it to map down to _sdata..._heap by reading this space
;
      MOV   ESI,_sdata
      MOV   ECX,_heap
      SUB   ECX,ESI
      SHR   ECX,2          ; we are reading DWORDs
      ADD   ECX,2          ; paranoic
      cld
      rep LODSD
;
; Disable the cache. This keeps it from shuffling data in and out,
; so now it is just like an 16K static RAM at location _sdata.
;
      mov   eax, cr0
      or    eax, 0x60000000
      mov   cr0, eax
[...]

Regards
Juergen

[Segher Boessenkool]

> When using cache as ram how can i ensure that the data in cache can  
> not be swapped out?

The most generic way is to just not access any cacheable space
that isn't in the cache yet.

Segher

[ollie]

On Thu, 2006-10-26 at 16:19 +0800, Jiangbo W wrote:
> Hi,
>
> When using cache as ram how can i ensure that the data in cache can
> not be swapped out?

The key (very confusing though) is the cache is actually "disabled" when
CAR is working. This prevents the data been flushed back to the main 
memory.

Ollie

[ron minnich]

I have sent Eswar's slides from last year's summit to stefan for posting on
the web page.

it turns out cache disable doesn't really mean cache disable -- that's the
confusing part.

thanks

ron

[Stefan Reinauer]

* ron minnich  [061026 21:20]:
> I have sent Eswar's slides from last year's summit to stefan for posting on the
> web page.

They're on the documentation page in the papers section.

Stefan