This is another milestone in my quest to obsolete v2.
[Patch looks strange due to a svn bug. Please let me commit, my tree will give us proper svn blame history and actually commit correctly.]
Compile tested. Untested on hardware, but it should work. Marc, can you please test on real hardware?
AMD DB800 support, ported from v2.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
--- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig 2008-03-04 03:07:01.000000000 +0100 @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config MAINBOARD_NAME + string + default amd/db800 + depends BOARD_AMD_DB800 + help + This is the default mainboard name. + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + # TODO: Fix PCI ID. + default 0x1022 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem vendor ID. + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + # TODO: Fix PCI ID. + default 0x2323 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem device ID. + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/initram.c 2008-03-04 04:02:32.000000000 +0100 @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <northbridge/amd/geodelx/raminit.h> + +/* #include <device/smbus.h> + * TODO: figure out how smbus functions should be done. See smbus_ops.c + */ +extern int smbus_read_byte(u16 device, u8 address); + +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRLO 0x02000030 +#define DIMM0 ((u8) 0xA0) +#define DIMM1 ((u8) 0xA2) + +u8 spd_read_byte(u16 device, u8 address) +{ + u8 spdbyte; + + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + + spdbyte = smbus_read_byte(device, address); + + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte); + + return spdbyte; +} + +/** + * Placeholder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +/** + * main for initram for the AMD DB800 development platform. + * It might seem that you could somehow do these functions in, e.g., the cpu + * code, but the order of operations and what those operations are is VERY + * strongly mainboard dependent. It's best to leave it in the mainboard code. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n"); + post_code(POST_START_OF_MAIN); + + system_preinit(); + printk(BIOS_DEBUG, "done preinit\n"); + + mb_gpio_init(); + printk(BIOS_DEBUG, "done gpio init\n"); + + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + printk(BIOS_DEBUG, "done pll reset\n"); + + cpu_reg_init(0, DIMM0, DIMM1); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram enable\n"); + + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/stage1.c 2008-03-04 03:05:09.000000000 +0100 @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> + +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); + geodelx_msr_init(); + + cs5536_stage1(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); + +} + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/dts 2008-03-04 04:01:49.000000000 +0100 @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard-vendor = "AMD"; + mainboard-name = "DB800"; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); + }; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); + }; + pci@15,0 { + /config/("southbridge/amd/cs5536/dts"); + enable_ide = "1"; + /* Interrupt enables for LPC bus. + * Each bit is an IRQ 0-15. */ + lpc_serirq_enable = "0x000010da"; + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ + lpc_serirq_polarity = "0x0000EF25"; + /* 0:continuous 1:quiet */ + lpc_serirq_mode = "1"; + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + * See virtual PIC spec. */ + enable_gpio_int_route = "0x0D0C0700"; + enable_USBP4_device = "1"; + }; + ioport@46 { + /config/("superio/winbond/w83627hf/dts"); + com1enable = "1"; + }; + }; +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h 2008-03-04 04:02:08.000000000 +0100 @@ -0,0 +1,81 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <pirq_routing.h> + +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 4 + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +/* + * AMD DB800 interrupt wiring. + * + * Devices are: + * + * FIXME + * + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* Checksum */ + { + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + + /* On-board ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* PCI (slot 1) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, + } +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/cmos.layout 2008-03-04 03:08:52.000000000 +0100 @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Makefile 2008-03-04 03:18:53.000000000 +0100 @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o + +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c + +STAGE2_MAINBOARD_OBJ = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Index: LinuxBIOSv3-db800/mainboard/amd/Kconfig =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/Kconfig (Revision 630) +++ LinuxBIOSv3-db800/mainboard/amd/Kconfig (Arbeitskopie) @@ -23,6 +23,18 @@ prompt "Mainboard model" depends on VENDOR_AMD
+config BOARD_AMD_DB800 + bool "DB800" + select ARCH_X86 + select CPU_AMD_GEODELX + select OPTION_TABLE + select NORTHBRIDGE_AMD_GEODELX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + help + AMD DB800 Geode LX development board. + config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86 @@ -36,5 +48,6 @@
endchoice
+source "mainboard/amd/db800/Kconfig" source "mainboard/amd/norwich/Kconfig"
Index: LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h (Revision 630) +++ LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h (Arbeitskopie) @@ -17,17 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h"
/* Number of slots and devices in the PIR table */ #define SLOT_COUNT 6 @@ -83,13 +73,19 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ - {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* slot1 */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, + /* slot2 */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, + /* slot3 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, + /* slot4 */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, } }; Index: LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig (Arbeitskopie) @@ -21,8 +21,8 @@
config MAINBOARD_NAME string - default amd/norwich - depends BOARD_AMD_NORWICH + default amd/db800 + depends BOARD_AMD_DB800 help This is the default mainboard name.
@@ -30,7 +30,7 @@ hex # TODO: Fix PCI ID. default 0x1022 - depends BOARD_AMD_NORWICH + depends BOARD_AMD_DB800 help Mainboard specific PCI subsystem vendor ID.
@@ -38,7 +38,7 @@ hex # TODO: Fix PCI ID. default 0x2323 - depends BOARD_AMD_NORWICH + depends BOARD_AMD_DB800 help Mainboard specific PCI subsystem device ID.
Index: LinuxBIOSv3-db800/mainboard/amd/db800/initram.c =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/initram.c (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/initram.c (Arbeitskopie) @@ -67,7 +67,7 @@ }
/** - * main for initram for the AMD Norwich development platform. + * main for initram for the AMD DB800 development platform. * It might seem that you could somehow do these functions in, e.g., the cpu * code, but the order of operations and what those operations are is VERY * strongly mainboard dependent. It's best to leave it in the mainboard code. Index: LinuxBIOSv3-db800/mainboard/amd/db800/dts =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/dts (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/dts (Arbeitskopie) @@ -19,8 +19,8 @@ */
/{ - mainboard-vendor = "PC Engines"; - mainboard-name = "ALIX1.C"; + mainboard-vendor = "AMD"; + mainboard-name = "DB800"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); @@ -45,6 +45,7 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; + enable_USBP4_device = "1"; }; ioport@46 { /config/("superio/winbond/w83627hf/dts"); Index: LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h (Arbeitskopie) @@ -19,12 +19,14 @@
#include <pirq_routing.h>
+/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 4
/* Platform IRQs */ -#define PIRQA 11 -#define PIRQB 10 -#define PIRQC 11 -#define PIRQD 9 +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11
/* Map */ #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ @@ -39,39 +41,18 @@ #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
/* - * ALIX1.C interrupt wiring. + * AMD DB800 interrupt wiring. * * Devices are: * - * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31) - * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block - * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) - * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01) - * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) - * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) - * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) - * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) - * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) + * FIXME * - * The only devices that interrupt are: - * - * What Device IRQ PIN PIN WIRED TO - * ------------------------------------------------- - * AES 00:01.2 0a 01 A A - * 3VPCI 00:0c.0 0a 01 A A - * eth0 00:0d.0 0b 01 A B - * mpci 00:0e.0 0a 01 A A - * usb 00:0f.3 0b 02 B B - * usb 00:0f.4 0b 04 D D - * usb 00:0f.5 0b 04 D D - * - * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B. */
const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -88,16 +69,13 @@ /* CPU */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
- /* PCI (slot 1) */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0}, + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
/* On-board ethernet */ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
- /* Mini PCI (slot 2) */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, - - /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* PCI (slot 1) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, } }; Index: LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h (Revision 630) +++ LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h (Arbeitskopie) @@ -19,6 +19,8 @@
#include <pirq_routing.h>
+/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 5
/* Platform IRQs */ #define PIRQA 11 @@ -71,7 +73,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */
Carl-Daniel Hailfinger wrote:
This is another milestone in my quest to obsolete v2.
[Patch looks strange due to a svn bug. Please let me commit, my tree will give us proper svn blame history and actually commit correctly.]
As you noted, reading the patch is weird. I don't understand, are you trying to keep file history from the original files or something? I would still expect the diff to have all new files. There is a second patch of the file that doesn't make sense. For example: LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h.
I couldn't get it to apply cleanly. Maybe my mail reader munged it. Can you check it applies and resend?
Also, there are some other cleanups that should probably be in a seperate patch. LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h
Marc
On 04.03.2008 18:46, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
This is another milestone in my quest to obsolete v2.
[Patch looks strange due to a svn bug. Please let me commit, my tree will give us proper svn blame history and actually commit correctly.]
As you noted, reading the patch is weird. I don't understand, are you trying to keep file history from the original files or something?
Yes.
I would still expect the diff to have all new files.
The new files (with svn cp) didn't appear at all. They were hand-diffed by me.
There is a second patch of the file that doesn't make sense. For example: LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h.
And that was an artifact of my process.
I couldn't get it to apply cleanly. Maybe my mail reader munged it. Can you check it applies and resend?
New patch, completely hand-generated, apply checked and compile checked.
Also, there are some other cleanups that should probably be in a seperate patch. LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h
Thanks, killed.
Regards, Carl-Daniel
AMD DB800 support, ported from v2.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
--- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig 2008-03-04 03:07:01.000000000 +0100 @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config MAINBOARD_NAME + string + default amd/db800 + depends BOARD_AMD_DB800 + help + This is the default mainboard name. + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + # TODO: Fix PCI ID. + default 0x1022 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem vendor ID. + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + # TODO: Fix PCI ID. + default 0x2323 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem device ID. + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/initram.c 2008-03-04 04:02:32.000000000 +0100 @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <northbridge/amd/geodelx/raminit.h> + +/* #include <device/smbus.h> + * TODO: figure out how smbus functions should be done. See smbus_ops.c + */ +extern int smbus_read_byte(u16 device, u8 address); + +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRLO 0x02000030 +#define DIMM0 ((u8) 0xA0) +#define DIMM1 ((u8) 0xA2) + +u8 spd_read_byte(u16 device, u8 address) +{ + u8 spdbyte; + + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + + spdbyte = smbus_read_byte(device, address); + + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte); + + return spdbyte; +} + +/** + * Placeholder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +/** + * main for initram for the AMD DB800 development platform. + * It might seem that you could somehow do these functions in, e.g., the cpu + * code, but the order of operations and what those operations are is VERY + * strongly mainboard dependent. It's best to leave it in the mainboard code. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n"); + post_code(POST_START_OF_MAIN); + + system_preinit(); + printk(BIOS_DEBUG, "done preinit\n"); + + mb_gpio_init(); + printk(BIOS_DEBUG, "done gpio init\n"); + + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + printk(BIOS_DEBUG, "done pll reset\n"); + + cpu_reg_init(0, DIMM0, DIMM1); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram enable\n"); + + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/stage1.c 2008-03-04 03:05:09.000000000 +0100 @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> + +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); + geodelx_msr_init(); + + cs5536_stage1(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); + +} + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/dts 2008-03-04 04:01:49.000000000 +0100 @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard-vendor = "AMD"; + mainboard-name = "DB800"; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); + }; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); + }; + pci@15,0 { + /config/("southbridge/amd/cs5536/dts"); + enable_ide = "1"; + /* Interrupt enables for LPC bus. + * Each bit is an IRQ 0-15. */ + lpc_serirq_enable = "0x000010da"; + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ + lpc_serirq_polarity = "0x0000EF25"; + /* 0:continuous 1:quiet */ + lpc_serirq_mode = "1"; + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + * See virtual PIC spec. */ + enable_gpio_int_route = "0x0D0C0700"; + enable_USBP4_device = "1"; + }; + ioport@46 { + /config/("superio/winbond/w83627hf/dts"); + com1enable = "1"; + }; + }; +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h 2008-03-04 04:02:08.000000000 +0100 @@ -0,0 +1,81 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <pirq_routing.h> + +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 4 + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +/* + * AMD DB800 interrupt wiring. + * + * Devices are: + * + * FIXME + * + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* Checksum */ + { + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + + /* On-board ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* PCI (slot 1) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, + } +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/cmos.layout 2008-03-04 03:08:52.000000000 +0100 @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Makefile 2008-03-04 03:18:53.000000000 +0100 @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o + +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c + +STAGE2_MAINBOARD_OBJ = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Index: LinuxBIOSv3-db800/mainboard/amd/Kconfig =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/Kconfig (Revision 630) +++ LinuxBIOSv3-db800/mainboard/amd/Kconfig (Arbeitskopie) @@ -23,6 +23,18 @@ prompt "Mainboard model" depends on VENDOR_AMD
+config BOARD_AMD_DB800 + bool "DB800" + select ARCH_X86 + select CPU_AMD_GEODELX + select OPTION_TABLE + select NORTHBRIDGE_AMD_GEODELX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + help + AMD DB800 Geode LX development board. + config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86 @@ -36,5 +48,6 @@
endchoice
+source "mainboard/amd/db800/Kconfig" source "mainboard/amd/norwich/Kconfig"
New patch, completely hand-generated, apply checked and compile checked.
I still had some issues getting the patch to apply. It could be my Thunderbird mail reader but you should check. Attaching the file would avoid a mail reader issue.
Problem in the dts
lpc_serirq_mode = "1";/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + *See virtual PIC spec. */
...
Problem in the Makefile
+STAGE2_MAINBOARD_OBJ = +
patch didn't like this like either. I had to put a space before config to get it to work.
config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86
It wouldn't boot all the way into Linux. It seems like there is a IRQ routing since that is where the image stopped. I attached db800 and norwich console output.
Marc
On 04.03.2008 22:09, Marc Jones wrote:
New patch, completely hand-generated, apply checked and compile checked.
I still had some issues getting the patch to apply. It could be my Thunderbird mail reader but you should check. Attaching the file would avoid a mail reader issue.
Patch attached. I use Seamonkey and the patch applied just fine after the roundtrip. Sorry for the inconvenience.
It wouldn't boot all the way into Linux. It seems like there is a IRQ routing since that is where the image stopped. I attached db800 and norwich console output.
Thanks. The IRQ routing was copied straight from v2 so there should be no difference in theory.
There are a few things I don't like about the boot log:
Done pll_reset done pll reset SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
All those SMBus error messages. Need to investigate.
Done cpubug fixes done cpu reg init done sdram set registers SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 ========== Check present ======================================================= ========== MODBANKS ============================================================ ========== FIELDBANKS ========================================================== ========== SPDNUMROWS ========================================================== ========== SPDBANKDENSITY ====================================================== ========== BEFORT CTZ ========================================================== ========== TEST DIMM SIZE>8 ==================================================== ========== PAGESIZE ============================================================ ========== MAXCOLADDR ========================================================== ========== RDMSR CF07 ========================================================== ========== WRMSR CF07 ========================================================== ========== ALL DONE ============================================================ ========== Check present ======================================================= SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13 done sdram set spd registers DRAM controller init done. RAM DLL lock done sdram enable stage1 returns run_file returns with 0 Done RAM init code
[...]
PCI: scan devfn 0x0 to 0xff PCI: devfn 0x0 pci_scan_get_dev: list is 0x00087eb4, *list is 0x0000b4c0 pci_scan_get_dev: check dev pci_1_0 pci_scan_get_dev: check dev pci_1_0 it has devfn 0x08 pci_scan_get_dev: check dev pci_15_0 pci_scan_get_dev: check dev pci_15_0 it has devfn 0x78 pci_scan_get_dev: check dev ioport_46 pci_scan_get_dev: child ioport_46(IOPORT: 2e) not a pci device: it's type 11 PCI: pci_scan_bus pci_scan_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev 0x00000000("�3 9�Gw�g�7����E�A�$@FP%{�Ճl����7B�f�� 1� ��" 0{�j����w�{� �.��4�xH`) PCI: devfn 0x8
And the above points to memory corruption or reading uninitialized memory. That's a bug.
PCI: devfn 0xb, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev 0x00000000("�3 9�Gw�g�7����E�A�$@FP%{�Ճl����7B�f�� 1� ��" 0{�j����w�{� �.��4�xH`) PCI: devfn 0xc
Same here. And countless repetitions.
Phase 4: Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1 cpus: Unknown device path type: 0 read_resources: cpus() missing phase4_read_resources read_resources: root(Root Device) dtsname apic_0 have_resources 0 enabled 1 read_resources: root(Root Device) dtsname domain_0 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname pci_1_0 have_resources 0 enabled 1 read_resources: "�3 9�Gw�g�7����E�A�$@FP%{�Ճl����7B�f�� 1� ��" 0{�j����w�{� �.��4�xH`(<null>) read_resources bus 0 link: 0 read_resources: "�3 9�Gw�g�7����E�A�$@FP%{�Ճl����7B�f�� 1� ��" 0{�j����w�{� �.��4�xH`(<null>) read_resources bus 0 link: 0 done read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:01.1 have_resources 0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:01.2 have_resources 0 enabled 1
Similar bug.
Copying IRQ routing tables to 0x983040x...done. Verifing copy of IRQ routing tables at 0x983040x...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x0x000f0000 /home/marcj/svn/coreboot-v3/arch/x86/pirq_routing.c: 62:check_pirq_routing_table() - checksum is: 0x00 but should be: 0x26 done.
Ouch. And I claim the table was a straight copy of the v2 db800 table...
Thanks a lot for testing! Could you maybe test v2 db800 as well to check IRQ routing tables consistency there?
Fixes for some of the bugs above will come in a separate patch.
Regards, Carl-Daniel
Carl-Daniel Hailfinger wrote:
On 04.03.2008 22:09, Marc Jones wrote: There are a few things I don't like about the boot log:
Done pll_reset done pll reset SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
All those SMBus error messages. Need to investigate.
It just means that there isn't a dimm there. Marc
On 04.03.2008 23:16, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
On 04.03.2008 22:09, Marc Jones wrote: There are a few things I don't like about the boot log:
Done pll_reset done pll reset SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
All those SMBus error messages. Need to investigate.
It just means that there isn't a dimm there.
Thanks for clearing this up. That means we have to work on the error messages. They are irritating and confusing. And they appear too often.
Regards, Carl-Daniel
Carl-Daniel Hailfinger wrote:
On 04.03.2008 23:16, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
On 04.03.2008 22:09, Marc Jones wrote: There are a few things I don't like about the boot log:
Done pll_reset done pll reset SMBus WAIT ERROR 13 SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
All those SMBus error messages. Need to investigate.
It just means that there isn't a dimm there.
Thanks for clearing this up. That means we have to work on the error messages. They are irritating and confusing. And they appear too often.
Regards, Carl-Daniel
They are turned up to level 8 (irritating and confusing). You wouldn't see that at level 4.....
Yes, that could be done better. My only excuse is that it was ported from stackless asm which couldn't track dimm presence.
Marc
On Tue, Mar 4, 2008 at 2:30 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Thanks for clearing this up. That means we have to work on the error messages. They are irritating and confusing. And they appear too often.
I agree. Somehow we need to balance need for lots of diags in SPEW with diags that are actually useful ...
ron
Can I have an Ack so we can work on the code in-tree?
AMD DB800 support, ported from v2. Tested on real hardware, some weirdness remains, probably related to IRQ routing.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
--- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig 2008-03-04 03:07:01.000000000 +0100 @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config MAINBOARD_NAME + string + default amd/db800 + depends BOARD_AMD_DB800 + help + This is the default mainboard name. + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + # TODO: Fix PCI ID. + default 0x1022 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem vendor ID. + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + # TODO: Fix PCI ID. + default 0x2323 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem device ID. + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/initram.c 2008-03-04 04:02:32.000000000 +0100 @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <northbridge/amd/geodelx/raminit.h> + +/* #include <device/smbus.h> + * TODO: figure out how smbus functions should be done. See smbus_ops.c + */ +extern int smbus_read_byte(u16 device, u8 address); + +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRLO 0x02000030 +#define DIMM0 ((u8) 0xA0) +#define DIMM1 ((u8) 0xA2) + +u8 spd_read_byte(u16 device, u8 address) +{ + u8 spdbyte; + + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + + spdbyte = smbus_read_byte(device, address); + + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte); + + return spdbyte; +} + +/** + * Placeholder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +/** + * main for initram for the AMD DB800 development platform. + * It might seem that you could somehow do these functions in, e.g., the cpu + * code, but the order of operations and what those operations are is VERY + * strongly mainboard dependent. It's best to leave it in the mainboard code. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n"); + post_code(POST_START_OF_MAIN); + + system_preinit(); + printk(BIOS_DEBUG, "done preinit\n"); + + mb_gpio_init(); + printk(BIOS_DEBUG, "done gpio init\n"); + + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + printk(BIOS_DEBUG, "done pll reset\n"); + + cpu_reg_init(0, DIMM0, DIMM1); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram enable\n"); + + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/stage1.c 2008-03-04 03:05:09.000000000 +0100 @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> + +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); + geodelx_msr_init(); + + cs5536_stage1(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); + +} + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/dts 2008-03-04 04:01:49.000000000 +0100 @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard-vendor = "AMD"; + mainboard-name = "DB800"; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); + }; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); + }; + pci@15,0 { + /config/("southbridge/amd/cs5536/dts"); + enable_ide = "1"; + /* Interrupt enables for LPC bus. + * Each bit is an IRQ 0-15. */ + lpc_serirq_enable = "0x000010da"; + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ + lpc_serirq_polarity = "0x0000EF25"; + /* 0:continuous 1:quiet */ + lpc_serirq_mode = "1"; + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + * See virtual PIC spec. */ + enable_gpio_int_route = "0x0D0C0700"; + enable_USBP4_device = "1"; + }; + ioport@46 { + /config/("superio/winbond/w83627hf/dts"); + com1enable = "1"; + }; + }; +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h 2008-03-04 04:02:08.000000000 +0100 @@ -0,0 +1,81 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <pirq_routing.h> + +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 4 + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +/* + * AMD DB800 interrupt wiring. + * + * Devices are: + * + * FIXME + * + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* Checksum */ + { + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + + /* On-board ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* PCI (slot 1) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, + } +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/cmos.layout 2008-03-04 03:08:52.000000000 +0100 @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Makefile 2008-03-04 03:18:53.000000000 +0100 @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o + +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c + +STAGE2_MAINBOARD_OBJ = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Index: LinuxBIOSv3-db800/mainboard/amd/Kconfig =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/Kconfig (Revision 630) +++ LinuxBIOSv3-db800/mainboard/amd/Kconfig (Arbeitskopie) @@ -23,6 +23,18 @@ prompt "Mainboard model" depends on VENDOR_AMD
+config BOARD_AMD_DB800 + bool "DB800" + select ARCH_X86 + select CPU_AMD_GEODELX + select OPTION_TABLE + select NORTHBRIDGE_AMD_GEODELX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + help + AMD DB800 Geode LX development board. + config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86 @@ -36,5 +48,6 @@
endchoice
+source "mainboard/amd/db800/Kconfig" source "mainboard/amd/norwich/Kconfig"
Carl-Daniel Hailfinger wrote:
Can I have an Ack so we can work on the code in-tree?
AMD DB800 support, ported from v2. Tested on real hardware, some weirdness remains, probably related to IRQ routing.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Sorry, I thought you were going to make more changes.
Acked-by: Marc Jones marc.jones@amd.com
On 14.03.2008 21:49, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
Can I have an Ack so we can work on the code in-tree?
AMD DB800 support, ported from v2. Tested on real hardware, some weirdness remains, probably related to IRQ routing.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Sorry, I thought you were going to make more changes.
Most of the changes I wanted were committed separately.
Acked-by: Marc Jones marc.jones@amd.com
Thanks, committed in r643.
It would be great, though, if we could find out why the v3 port behaves weirdly although IRQ tables are exactly the same as in v2. It would be great if you could find some time to investigate that.
Regards, Carl-Daniel
On Fri, Mar 14, 2008 at 1:29 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
It would be great, though, if we could find out why the v3 port behaves weirdly although IRQ tables are exactly the same as in v2. It would be great if you could find some time to investigate that.
yes. There is something wrong with interrupts. Or something. MFGPT does not work on alix1c, ISDN has some weird IRQ problem.
There's something just not right, but I can't see it.
ron
On 04.03.2008 22:09, Marc Jones wrote:
It wouldn't boot all the way into Linux. It seems like there is a IRQ routing since that is where the image stopped. I attached db800 and norwich console output.
Thanks for the output. I don't like a few parts of the db800 output which are not there on norwich:
PCI: Done for loop ioport_46 ========== PCI: Left over static devices. =====================================
It complains about left over devices, but the only leftover device is not a PCI device as far as the logs seem to tell. Could be a bug, could be that the db800 and norwich have different sets of PCI devices showing up... Hm. Need to find out why dev_find_device on db800 is called 3 times for 1022:2097 and 2 times for 1022:2096, all of them in phase 6. On Norwich, dev_find_device is called 2 times for 1022:2097 and once for 1022:2096.
db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2095 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2095 norwich.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2096 norwich.txt:dev_find_device: find PCI: 1022:2097
More analysis later.
Regards, Carl-Daniel
On Tue, Mar 4, 2008 at 5:35 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
It complains about left over devices, but the only leftover device is not a PCI device as far as the logs seem to tell. Could be a bug, could be that the db800 and norwich have different sets of PCI devices showing up...
It is a factor of the pci-centric nature of the old v2 device tree.
Needs cleanup.
Hm. Need to find out why dev_find_device on db800 is called 3 times for 1022:2097 and 2 times for 1022:2096, all of them in phase 6. On Norwich, dev_find_device is called 2 times for 1022:2097 and once for 1022:2096.
db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2095 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2095 norwich.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2096 norwich.txt:dev_find_device: find PCI: 1022:2097
More analysis later.
it's an nxm algorithm. I am pretty sure those multilple prints of same device are the devices in the tree it is trying to match against, not the device it is called with.
ron
On 05.03.2008 03:56, ron minnich wrote:
On Tue, Mar 4, 2008 at 5:35 PM, Carl-Daniel Hailfinger wrote:
It complains about left over devices, but the only leftover device is not a PCI device as far as the logs seem to tell. Could be a bug, could be that the db800 and norwich have different sets of PCI devices showing up...
It is a factor of the pci-centric nature of the old v2 device tree.
Needs cleanup.
Can you do that? I'm not totally familiar with the code there.
Hm. Need to find out why dev_find_device on db800 is called 3 times for 1022:2097 and 2 times for 1022:2096, all of them in phase 6. On Norwich, dev_find_device is called 2 times for 1022:2097 and once for 1022:2096.
db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2095 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2095 norwich.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2096 norwich.txt:dev_find_device: find PCI: 1022:2097
More analysis later.
it's an nxm algorithm. I am pretty sure those multilple prints of same device are the devices in the tree it is trying to match against, not the device it is called with.
No, unfortunately this is the device it is called with/looking for. Seems to be a bug.
Regards, Carl-Daniel
Ron?
On 05.03.2008 14:04, Carl-Daniel Hailfinger wrote:
On 05.03.2008 03:56, ron minnich wrote:
On Tue, Mar 4, 2008 at 5:35 PM, Carl-Daniel Hailfinger wrote:
It complains about left over devices, but the only leftover device is not a PCI device as far as the logs seem to tell. Could be a bug, could be that the db800 and norwich have different sets of PCI devices showing up...
It is a factor of the pci-centric nature of the old v2 device tree.
Needs cleanup.
Can you do that? I'm not totally familiar with the code there.
Hm. Need to find out why dev_find_device on db800 is called 3 times for 1022:2097 and 2 times for 1022:2096, all of them in phase 6. On Norwich, dev_find_device is called 2 times for 1022:2097 and once for 1022:2096.
db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2090 db800.txt:dev_find_device: find PCI: 1022:2095 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 db800.txt:dev_find_device: find PCI: 1022:2096 db800.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2090 norwich.txt:dev_find_device: find PCI: 1022:2095 norwich.txt:dev_find_device: find PCI: 1022:2097 norwich.txt:dev_find_device: find PCI: 1022:2096 norwich.txt:dev_find_device: find PCI: 1022:2097
More analysis later.
it's an nxm algorithm. I am pretty sure those multilple prints of same device are the devices in the tree it is trying to match against, not the device it is called with.
No, unfortunately this is the device it is called with/looking for. Seems to be a bug.
Regards, Carl-Daniel
-
Carl-Daniel Hailfinger -
Marc Jones -
ron minnich