Personal challenge | Ramp up on coreboot : Trials on aftermarket X58 motherboards.

[Master]

Hello everyone,

I hope you're doing fine

I would like to do some trials to see if I may be able to support few boards I have cause they are aftermarket withoout EFI and without firmware updates and not working as I would like them to.
(https://askubuntu.com/questions/1370496/cant-boot-latests-lives-for-install-...)
I really would not like to throw them...

They are X58 chipset with ICH10  with Xeon Westmere on socket 1366 and SuperIO NCT5532D.
(https://www.intel.com/content/dam/doc/datasheet/x58-express-chipset-datashee...)
(https://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-...)
(https://datasheetspdf.com/pdf-file/1042365/novoTon/NCT5532D/1)

I have the tooling to backup and restore the flash and already done that few time.
I have built latest coreboot (4.14 using lenovo x201 config) with EDK2 firmware as payload (edk2-stable202108 NOOPT) successfully but nothing is happening after flash swap and power on.

I have RS232 debug working at ttyS0 (at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A)
From the original firmware, just after power on, even before any bip or display or keyboard light I see "Socket = 0" on serial, so the the original firmware is able to output to this serial very early.

I read quite a lot of literature about coreboot, but still, I am not sure how to pursue now.

Thanks in advance,
Have a nice day,
Best Regards,
Mickaël.

[Angel Pons]

Hi Mickaël,

On Tue, Nov 23, 2021 at 11:29 AM Master <[e-mail]> wrote:
> Hello everyone,
>
> I hope you're doing fine
>
> I would like to do some trials to see if I may be able to support few boards I have cause they are aftermarket withoout EFI and without firmware updates and not working as I would like them to.
> (https://askubuntu.com/questions/1370496/cant-boot-latests-lives-for-install-...)
> I really would not like to throw them...
>
> They are X58 chipset with ICH10  with Xeon Westmere on socket 1366 and SuperIO NCT5532D.
> (https://www.intel.com/content/dam/doc/datasheet/x58-express-chipset-datashee...)
> (https://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-...)
> (https://datasheetspdf.com/pdf-file/1042365/novoTon/NCT5532D/1)

Only the ICH10 southbridge (southbridge/intel/i82801jx) is currently
supported. Neither the CPU nor the X58 IOH are supported. Most of the
complexity is RAM initialization, especially because Intel does not
publicly document the relevant registers. It would likely take years
for an experienced developer to implement RAM init in coreboot.

The NCT5532D Super I/O isn't supported either, but it's easy to add
support for it using the datasheet.
> I have the tooling to backup and restore the flash and already done that few time.
> I have built latest coreboot (4.14 using lenovo x201 config) with EDK2 firmware as payload (edk2-stable202108 NOOPT) successfully but nothing is happening after flash swap and power on.

Flashing a firmware image for a different board is a bad idea. In
extreme cases, incompatible GPIO configuration can result in
short-circuits. It's unlikely, though.
> I have RS232 debug working at ttyS0 (at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A)
> From the original firmware, just after power on, even before any bip or display or keyboard light I see "Socket = 0" on serial, so the the original firmware is able to output to this serial very early.
>
> I read quite a lot of literature about coreboot, but still, I am not sure how to pursue now.

It's hard. I can give you general ideas on how to proceed (I'm pretty
sure we can get coreboot to print something over RS232), but RAM init
is still a major roadblock. Once serial output is working, it's
possible to use SerialICE to gather useful information to reimplement
RAM init.
> Thanks in advance,
> Have a nice day,
> Best Regards,
> Mickaël.
> _______________________________________________
> coreboot mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

Best regards,
Angel

[Master]

Hi Angel,

I hope you're doing fine!

Thanks for your answer!

Ouch, hum, okay, understood...
So RAM init is more easy on already supported hardware?
What would be the effort to reach at least serialICE?

Thanks in advance,
Have a nice day,
Best Regards,
Mickaël.

________________________________________
De : Angel Pons <[e-mail]>
Envoyé : mercredi 24 novembre 2021 00:50
À : Master
Cc : [e-mail]
Objet : Re: [coreboot] Personal challenge | Ramp up on coreboot : Trials on aftermarket X58 motherboards.

Hi Mickaël,

On Tue, Nov 23, 2021 at 11:29 AM Master <[e-mail]> wrote:
> Hello everyone,
>
> I hope you're doing fine
>
> I would like to do some trials to see if I may be able to support few boards I have cause they are aftermarket withoout EFI and without firmware updates and not working as I would like them to.
> (https://askubuntu.com/questions/1370496/cant-boot-latests-lives-for-install-...)
> I really would not like to throw them...
>
> They are X58 chipset with ICH10  with Xeon Westmere on socket 1366 and SuperIO NCT5532D.
> (https://www.intel.com/content/dam/doc/datasheet/x58-express-chipset-datashee...)
> (https://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-...)
> (https://datasheetspdf.com/pdf-file/1042365/novoTon/NCT5532D/1)

Only the ICH10 southbridge (southbridge/intel/i82801jx) is currently
supported. Neither the CPU nor the X58 IOH are supported. Most of the
complexity is RAM initialization, especially because Intel does not
publicly document the relevant registers. It would likely take years
for an experienced developer to implement RAM init in coreboot.

The NCT5532D Super I/O isn't supported either, but it's easy to add
support for it using the datasheet.
> I have the tooling to backup and restore the flash and already done that few time.
> I have built latest coreboot (4.14 using lenovo x201 config) with EDK2 firmware as payload (edk2-stable202108 NOOPT) successfully but nothing is happening after flash swap and power on.

Flashing a firmware image for a different board is a bad idea. In
extreme cases, incompatible GPIO configuration can result in
short-circuits. It's unlikely, though.
> I have RS232 debug working at ttyS0 (at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A)
> From the original firmware, just after power on, even before any bip or display or keyboard light I see "Socket = 0" on serial, so the the original firmware is able to output to this serial very early.
>
> I read quite a lot of literature about coreboot, but still, I am not sure how to pursue now.

It's hard. I can give you general ideas on how to proceed (I'm pretty
sure we can get coreboot to print something over RS232), but RAM init
is still a major roadblock. Once serial output is working, it's
possible to use SerialICE to gather useful information to reimplement
RAM init.
> Thanks in advance,
> Have a nice day,
> Best Regards,
> Mickaël.
> _______________________________________________
> coreboot mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

Best regards,
Angel

[Patrick Zacharias]

Hi Mickaël,

I've been trying myself to port coreboot to a new motherboard.
Luckily in my case however there is documentation available.
As I'm a beginner myself please take everything I say with a grain of salt.

Getting SerialICE to work is fairly straight forward, in my opinion.
You "just" need to get the Super I/O to work.

Assuming you have documentation on that,
it usually boils down to "just" setting the correct registers.
Some Super I/O chips require you to put them into a config mode first 
(called "extended function mode"),
which is where the documentation or code of similar Super I/Os comes in 
handy.

To probe the contents I've written a simple FreeDOS application,
that prints the registers and remapped the I/O port address of the 
serial port to a different address.
Then I debugged it by doing a test print there using "outb".

As long as your fans are spinning automatically on power up that should 
be everything you need to get SerialICE running, as far as I know.

In my case the biggest holdup was an array that's expected to be at a 
certain location in the flash, that is being used to initialize the 
hardware, before the CPU even runs.
Therefor I probably had badly configured clocks and all my debug outputs 
using post were garbage.
Apparently that array is called "romstrap" and is usually located near 
the end of the file containing the BIOS.

Btw., there is a dedicated wiki page for SerialICE.
https://www.serialice.com/Make_SerialICE_work_on_new_hardware

Greetings,
Patrick


Am 28.11.21 um 00:10 schrieb Master:
> Hi Angel,
>
> I hope you're doing fine!
>
> Thanks for your answer!
>
> Ouch, hum, okay, understood...
> So RAM init is more easy on already supported hardware?
> What would be the effort to reach at least serialICE?
>
> Thanks in advance,
> Have a nice day,
> Best Regards,
> Mickaël.
>
> ________________________________________
> De : Angel Pons <[e-mail]>
> Envoyé : mercredi 24 novembre 2021 00:50
> À : Master
> Cc : [e-mail]
> Objet : Re: [coreboot] Personal challenge | Ramp up on coreboot : Trials on aftermarket X58 motherboards.
>
> Hi Mickaël,
>
> On Tue, Nov 23, 2021 at 11:29 AM Master <[e-mail]> wrote:
> > Hello everyone,
> >
> > I hope you're doing fine
> >
> > I would like to do some trials to see if I may be able to support few boards I have cause they are aftermarket withoout EFI and without firmware updates and not working as I would like them to.
> > (https://askubuntu.com/questions/1370496/cant-boot-latests-lives-for-install-...)
> > I really would not like to throw them...
> >
> > They are X58 chipset with ICH10  with Xeon Westmere on socket 1366 and SuperIO NCT5532D.
> > (https://www.intel.com/content/dam/doc/datasheet/x58-express-chipset-datashee...)
> > (https://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-...)
> > (https://datasheetspdf.com/pdf-file/1042365/novoTon/NCT5532D/1)
> > Only the ICH10 southbridge (southbridge/intel/i82801jx) is currently
> > supported. Neither the CPU nor the X58 IOH are supported. Most of the
> > complexity is RAM initialization, especially because Intel does not
> > publicly document the relevant registers. It would likely take years
> > for an experienced developer to implement RAM init in coreboot.
>
> The NCT5532D Super I/O isn't supported either, but it's easy to add
> support for it using the datasheet.
> > I have the tooling to backup and restore the flash and already done that few time.
> > I have built latest coreboot (4.14 using lenovo x201 config) with EDK2 firmware as payload (edk2-stable202108 NOOPT) successfully but nothing is happening after flash swap and power on.
> > Flashing a firmware image for a different board is a bad idea. In
> > extreme cases, incompatible GPIO configuration can result in
> > short-circuits. It's unlikely, though.
> > I have RS232 debug working at ttyS0 (at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A)
> >  From the original firmware, just after power on, even before any bip or display or keyboard light I see "Socket = 0" on serial, so the the original firmware is able to output to this serial very early.
> >
> > I read quite a lot of literature about coreboot, but still, I am not sure how to pursue now.
> > It's hard. I can give you general ideas on how to proceed (I'm pretty
> > sure we can get coreboot to print something over RS232), but RAM init
> > is still a major roadblock. Once serial output is working, it's
> > possible to use SerialICE to gather useful information to reimplement
> > RAM init.
> > Thanks in advance,
> > Have a nice day,
> > Best Regards,
> > Mickaël.
> > _______________________________________________
> > coreboot mailing list -- [e-mail]
> > To unsubscribe send an email to [e-mail]
> > Best regards,
> > Angel
>
> coreboot mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]