[v2] r4389 - in trunk/coreboot-v2/src: include/device mainboard/via/epia-n southbridge/via/vt8237r

Author: rminnich
Date: 2009-07-01 15:19:25 +0200 (Wed, 01 Jul 2009)
New Revision: 4389

Modified:
   trunk/coreboot-v2/src/include/device/pci_ids.h
   trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
   trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
Log:
I missed three files. 
Signed-off-by: Jon Harrison 
Acked-by: Ronald G. Minnich

Modified: trunk/coreboot-v2/src/include/device/pci_ids.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-01 12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/include/device/pci_ids.h	2009-07-01 13:19:25 UTC (rev 4389)
@@ -1198,6 +1198,14 @@
 #define PCI_DEVICE_ID_VIA_CN700_VLINK	0x7314
 #define PCI_DEVICE_ID_VIA_CN700_BRIDGE	0xB198
 #define PCI_DEVICE_ID_VIA_CN700_VGA	0x3344
+#define PCI_DEVICE_ID_VIA_CN400_AGP	0x0259
+#define PCI_DEVICE_ID_VIA_CN400_ERR	0x1259
+#define PCI_DEVICE_ID_VIA_CN400_HOST	0x2259
+#define PCI_DEVICE_ID_VIA_CN400_MEMCTRL	0x3259
+#define PCI_DEVICE_ID_VIA_CN400_PM	0x4259
+#define PCI_DEVICE_ID_VIA_CN400_VLINK	0x7259
+#define PCI_DEVICE_ID_VIA_CN400_BRIDGE	0xB198
+#define PCI_DEVICE_ID_VIA_CN400_VGA	0x3118

#define PCI_VENDOR_ID_SIEMENS           0x110A
 #define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102

Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	2009-07-01 12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb	2009-07-01 13:19:25 UTC (rev 4389)
@@ -58,7 +58,7 @@
 uses CONFIG_HAVE_ACPI_RESUME
 uses CONFIG_CROSS_COMPILE
 uses CC
-uses CONFIG_HOSTCC
+uses HOSTCC
 uses CONFIG_OBJCOPY
 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
@@ -108,7 +108,7 @@
 default CONFIG_ROM_PAYLOAD = 1
 default CONFIG_CROSS_COMPILE = ""
 default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default CONFIG_HOSTCC = "gcc"
+default HOSTCC = "gcc"
 #default CONFIG_MAINBOARD = "EPIA-N"

##

Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2009-07-01 12:26:11 UTC (rev 4388)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c	2009-07-01 13:19:25 UTC (rev 4389)
@@ -91,7 +91,7 @@

/* All delivered to CPU0. */
    ioapic_table[0].value_high = (lapicid()) << (56 - 32);
-	l = (unsigned long *)ioapic_base;
+	l = (u32 *)ioapic_base;

/* Set APIC to FSB message bus. */
    l[0] = 0x3;
@@ -243,26 +243,56 @@
 {
    u8 enables;

+	printk_spew("Entering vt8237r_init.\n");
+	
+#ifdef CONFIG_EPIA_VT8237R_INIT
+	printk_spew("vt8237r_init SATA LED.\n");
    /*
+	 * TODO: Looks like stock BIOS can do this but causes a hang
     * Enable SATA LED, disable special CPU Frequency Change -
     * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 * Setup to match EPIA default
+	 * PCS0# on Pin U1
     */
-	pci_write_config8(dev, 0xe5, 0x9);
+	enables = pci_read_config8(dev, 0xe5);
+	enables |= 0x02;
+	pci_write_config8(dev, 0xe5, enables);
+	
+	printk_spew("vt8237r_init PCI Req.\n");
+	/* 
+	 * Enable Flash Write Access. 
+	 * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
+	 */
+	enables = pci_read_config8(dev, 0xe4);
+	enables |= 0x2B;
+	pci_write_config8(dev, 0xe4, enables);

+#else 
+	/*
+	 * Enable SATA LED, disable special CPU Frequency Change -
+	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+	 */
+	pci_write_config8(dev, 0xe5, 0x09);
+	
    /* REQ5 as PCI request input - should be together with INTE-INTH. */
    pci_write_config8(dev, 0xe4, 0x4);
+#endif

+
+	printk_spew("vt8237r_init CPU Rst.\n");
    /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
    enables = pci_read_config8(dev, 0x4f);
    enables |= 0x08;
    pci_write_config8(dev, 0x4f, enables);

+	printk_spew("vt8237r_init Read Pass Write Ctrl.\n");
    /*
     * Set Read Pass Write Control Enable
     * (force A2 from APIC FSB to low).
     */
    pci_write_config8(dev, 0x48, 0x8c);

+	printk_spew("vt8237r_init calling southbridge_init_common.\n");
    southbridge_init_common(dev);

/* FIXME: Intel needs more bit set for C2/C3. */
@@ -272,6 +302,8 @@
     * Will work for C3 and for FID/VID change.
     */
    outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+	
+	printk_spew("Leaving vt8237r_init.\n");
 }

static void vt8237s_init(struct device *dev)